8(RX 1,Toradex Colibri iMX8QXP on Colibri Iris V2 Board@2toradex,colibri-imx8x-iris-v2toradex,colibri-imx8xfsl,imx8qxpaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000/bus@5a000000/i2c@5a800000/bus@5a000000/i2c@5a810000/bus@5a000000/i2c@5a820000/bus@5a000000/i2c@5a830000/bus@5b000000/mmc@5b010000/bus@5b000000/mmc@5b020000/bus@5b000000/mmc@5b030000/bus@5d000000/mailbox@5d1b0000/bus@5d000000/mailbox@5d1c0000/bus@5d000000/mailbox@5d1d0000/bus@5d000000/mailbox@5d1e0000/bus@5d000000/mailbox@5d1f0000/bus@5a000000/serial@5a060000/bus@5a000000/serial@5a070000/bus@5a000000/serial@5a080000/bus@5a000000/serial@5a090000 /vpu@2c000000/vpu-core@2d080000 /vpu@2c000000/vpu-core@2d090000"/bus@5a000000/i2c@5a810000/rtc@68/system-controller/rtccpus cpu@0cpu2arm,cortex-a35psci!@3@M@_l } cpu@1cpu2arm,cortex-a35psci!@3@M@_l } cpu@2cpu2arm,cortex-a35psci!@3@M@_l } cpu@3cpu2arm,cortex-a35psci!@3@M@_l } l2-cache02cache#@5opp-table2operating-points-v2opp-9000000005B@Iopp-1200000000GIinterrupt-controller@51a00000 2arm,gic-v3 QQ  , reserved-memory 7decoder-boot@84000000>encoder-boot@86000000 >decoder-rpc@92000000>dsp@92400000@> Edisabledencoder-rpc@94400000@p>pmu2arm,cortex-a35-pmu ,psci 2arm,psci-1.0 smcsystem-controller 2fsl,imx-scu Ltx0rx0gip3$Wpower-controller2fsl,imx8qxp-scu-pdfsl,scu-pd^clock-controller2fsl,imx8qxp-clkfsl,scu-clkrpinctrl2fsl,imx8qxp-iomuxcdefaultRad7879intgrp !)adc0grp0d`c`h`g`atmeladaptergrpN!M!atmelconnectorgrp!!canintgrp @csictlgrp  csimclkgrp Aextio0grp 1@fec1grpx5 4 &a%a'a(a-a.a/a0aBfec1slpgrpx5A4A&A%A'A(A-A.A/A0ACflexcan0grpj!i!flexcan1grpl!k!flexcan2grpn!m!gpioblongrp `gpiohpdgrp z gpiokeysgrp pAThog0grpa S a, a T a U aR a      X   hog1grp  hog2grp  hogscfwgrp  i2c0grp!!'i2c0mipilvds0grpt u i2c0mipilvds1grpx y i2c1grpv!w!,lcdifgrp,L`H`K`J@@7``8`9`:`;`<`=`>`?`@`A`B`C`E`F`G`I`)`P`lpspi2grp0Y!Z@[@\@lpspi2cs2grp *!lpuart0grp0o p i j lpuart2grpr q  lpuart3grpm n "lpuart3ctrlgrpH{ V W    #pciebgrp$aa`pwmagrpa``pwmbgrp M`Lpwmcgrp N`NpwmdgrpaO`Psai0grp0^@a@]@_@sgtl5000grp Asgtl5000usbclkgrp e!(usb3503agrp ausbcdetgrp 3@usbh1reggrp @usdhc1grp A ! ! ! !!!!!!A!5usdhc1-100mhzgrp A ! ! ! !!!!!!A!6usdhc1-200mhzgrp A ! ! ! !!!!!!A!7usdhc2gpiogrp !;usdhc2gpioslpgrp `?usdhc2grpTA! !!!"!#!!:usdhc2-100mhzgrpTA! !!!"!#!!<usdhc2-200mhzgrpTA! !!!"!#!!=usdhc2slpgrpT`` `!`"`#`!>wifigrp  gpioirisgrpT  R U T , S uart1forceoffgrp  uart23forceoffgrp { enable-3v3-vmmc-grp X Ulvds-converter-grp0l k   ocotp2fsl,imx8qxp-scu-ocotp keys"2fsl,imx8qxp-sc-keyfsl,imx-sc-keyt Edisabledrtc2fsl,imx8qxp-sc-rtcwatchdog"2fsl,imx8qxp-sc-wdtfsl,imx-sc-wdt<thermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermaltimer2arm,armv8-timer0,   clock-xtal32k 2fixed-clockr xtal_32KHzclock-xtal24m 2fixed-clockrn6 xtal_24MHzthermal-zonescpu0-thermal ctripstrip0(_4passive trip1((4 criticalcooling-mapsmap0? 0D clock-img-ipg 2fixed-clockr  img_ipg_clkbus@58000000 2simple-bus 7XXjpegdec@58400000X@ ,5}Speripg_o 2nxp,imx8qxp-jpgdecEokayjpegenc@58450000XE ,1}Speripg_o 2nxp,imx8qxp-jpgencEokayclock-controller@585d00002fsl,imx8qxp-lpcgX]r}0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkclock-controller@585f00002fsl,imx8qxp-lpcgX_r}0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkvpu@2c000000 7,,, Edisabledmailbox@2d0000002fsl,imx6sx-mu- , Edisabledmailbox@2d0200002fsl,imx6sx-mu- , Edisabledvpu-core@2d080000-2nxp,imx8q-vpu-decoder Ltx0tx1rx$W Edisabledvpu-core@2d090000-2nxp,imx8q-vpu-encoder Ltx0tx1rx$W Edisabledclock-audio-ipg 2fixed-clockr'audio_ipg_clkbus@59000000 2simple-bus 7YYdma-controller@591f00002fsl,imx8qm-edmaY\  ,vwxyz{;;==?D@ABCDEFGHIJKLMNOPQRSTUVWclock-controller@595900002fsl,imx8qxp-lpcgYYr}dsp_ram_lpcg_ipg_clkdma-controller@599f00002fsl,imx8qm-edmaY  ,~JJLXlmnopqrstuvclock-dma-ipg 2fixed-clockr' dma_ipg_clk%bus@5a000000 2simple-bus 7ZZspi@5a0000002fsl,imx7ulp-spiZ  ,P}Speripg _5o5 Edisabledspi@5a0100002fsl,imx7ulp-spiZ  ,Q}Speripg _6o6 Edisabledspi@5a0200002fsl,imx7ulp-spiZ  ,R}Speripg _7o7Eokaydefault spi@5a0300002fsl,imx7ulp-spiZ  ,S}Speripg _8o8 Edisabledserial@5a060000Z ,Y} Sipgbaud _9oĴ9txrx  Eokay2fsl,imx8qxp-lpuartdefaultserial@5a070000Z ,Z} Sipgbaud _:oĴ:txrx    Edisabled2fsl,imx8qxp-lpuartserial@5a080000Z ,[} Sipgbaud _;oĴ;txrx   Eokay2fsl,imx8qxp-lpuartdefault serial@5a090000Z  ,\}!! Sipgbaud _<oĴ<txrx Eokay2fsl,imx8qxp-lpuartdefault"#pwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwmZ ,}$$Sipgper _on6dma-controller@5a1f00002fsl,imx8qm-edmaZ,dma-controller@5a9f00002fsl,imx8qm-edmaZ `,@clock-controller@5a4000002fsl,imx8qxp-lpcgZ@r}5% spi0_lpcg_clkspi0_lpcg_ipg_clk5clock-controller@5a4100002fsl,imx8qxp-lpcgZAr}6% spi1_lpcg_clkspi1_lpcg_ipg_clk6clock-controller@5a4200002fsl,imx8qxp-lpcgZBr}7% spi2_lpcg_clkspi2_lpcg_ipg_clk7clock-controller@5a4300002fsl,imx8qxp-lpcgZCr}8% spi3_lpcg_clkspi3_lpcg_ipg_clk8clock-controller@5a4600002fsl,imx8qxp-lpcgZFr}9%'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk9clock-controller@5a4700002fsl,imx8qxp-lpcgZGr}:%'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk:clock-controller@5a4800002fsl,imx8qxp-lpcgZHr};%'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk;clock-controller@5a4900002fsl,imx8qxp-lpcgZIr}<%'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk<!clock-controller@5a5900002fsl,imx8qxp-lpcgZYr}%(adma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clk$i2c@5a800000Z@ ,}&&Speripg _`on6`Eokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c default'(touchscreen@2c 2adi,ad7879-1default),*,x-H]t Edisabledi2c@5a810000Z@ ,}++Speripg _aon6aEokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c default,rtc@68 2st,m41t0hi2c@5a820000Z@ ,}--Speripg _bon6b Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ ,}..Speripg _con6c Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcZ ,}//Speripg _eon6e Edisabledcan@5a8d00002fsl,imx8qm-flexcanZ ,}00Sipgper _iobZi Edisabledcan@5a8e00002fsl,imx8qm-flexcanZ ,}00Sipgper _iobZj Edisabledcan@5a8f00002fsl,imx8qm-flexcanZ ,}00Sipgper _iobZk Edisabledclock-controller@5ac000002fsl,imx8qxp-lpcgZr}`% i2c0_lpcg_clki2c0_lpcg_ipg_clk`&clock-controller@5ac100002fsl,imx8qxp-lpcgZr}a% i2c1_lpcg_clki2c1_lpcg_ipg_clka+clock-controller@5ac200002fsl,imx8qxp-lpcgZr}b% i2c2_lpcg_clki2c2_lpcg_ipg_clkb-clock-controller@5ac300002fsl,imx8qxp-lpcgZr}c% i2c3_lpcg_clki2c3_lpcg_ipg_clkc.clock-controller@5ac800002fsl,imx8qxp-lpcgZr}e% adc0_lpcg_clkadc0_lpcg_ipg_clke/clock-controller@5acd00002fsl,imx8qxp-lpcgZr}i%% 5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clki0clock-conn-axi 2fixed-clockrCU conn_axi_clkIclock-conn-ahb 2fixed-clockr ! conn_ahb_clkJclock-conn-ipg 2fixed-clockr conn_ipg_clkHbus@5b000000 2simple-bus 7[[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[  , 12}3 Edisabledusbmisc@5b0d020082fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ 2usbphy@5b1000002fsl,imx7ulp-usbphy[}3 Edisabled1mmc@5b010000 ,[}444 SipgahbperEokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc&0>D"defaultstate_100mhzstate_200mhz5L6V7mmc@5b020000 ,[}888 Sipgahbper`uEokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhc& * 9(defaultstate_100mhzstate_200mhzsleep:;L<;V=;>?mmc@5b030000 ,[}@@@ Sipgahbper Edisabled"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0, }AAA ASipgahbenet_clk_refptp_o沀sY@Eokay.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecdefaultsleepBLCrmiiDmdio ethernet-phy@22ethernet-phy-ieee802.3-c22 dDethernet@5b050000[0, }EEE ESipgahbenet_clk_refptp_o沀sY@ Edisabled.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecusb@5b1100002fsl,imx8qm-usb3[ 7(}FFFFFSlpmbusaclkipgcore _o沀 Edisabledusb@5b120000 2cdns,usb3[[[ otgxhcidev0,hostperipheralotgwakeup/G4cdns3,usb3-phy> Edisabledusb-phy@5b1600002nxp,salvo-phy[}FSsalvo_phy_clkU EdisabledGclock-controller@5b2000002fsl,imx8qxp-lpcg[ r}HI 9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk4clock-controller@5b2100002fsl,imx8qxp-lpcg[!r}HI 9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk8clock-controller@5b2200002fsl,imx8qxp-lpcg["r}HI 9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk@clock-controller@5b2300002fsl,imx8qxp-lpcg[#r0}IHH enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkAclock-controller@5b2400002fsl,imx8qxp-lpcg[$r0}IHH enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkEclock-controller@5b2700002fsl,imx8qxp-lpcg['r}JH"usboh3_ahb_clkusboh3_phy_ipg_clk3clock-controller@5b2800002fsl,imx8qxp-lpcg[(r0}HHHMusb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclkFbus@5c000000 2simple-bus 7\\ddr-pmu@5c0200002fsl,imx8-ddr-pmu\ ,clock-lsio-bus 2fixed-clockr lsio_bus_clkSbus@5d000000 2simple-bus  7]]pwm@5d0000002fsl,imx27-pwm]Sipgper}KK _on6 ,^EokayLdefaultpwm@5d0100002fsl,imx27-pwm]Sipgper}MM _on6 ,_EokayNdefaultpwm@5d0200002fsl,imx27-pwm]Sipgper}OO _on6 ,`EokayPdefaultpwm@5d0300002fsl,imx27-pwm]Sipgper}QQ _on6 ,a Edisabledgpio@5d080000] ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpioP|R8 R ERKRPRRSODIMM_70SODIMM_60SODIMM_58SODIMM_78SODIMM_72SODIMM_80SODIMM_46SODIMM_62SODIMM_48SODIMM_74SODIMM_50SODIMM_52SODIMM_54SODIMM_66SODIMM_64SODIMM_68SODIMM_82SODIMM_56SODIMM_28SODIMM_30SODIMM_61SODIMM_103SODIMM_25SODIMM_27SODIMM_100Vgpio@5d090000]  ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpio0|RY R cRt SODIMM_86SODIMM_92SODIMM_90SODIMM_88SODIMM_59SODIMM_6SODIMM_8SODIMM_2SODIMM_4SODIMM_34SODIMM_32SODIMM_63SODIMM_55SODIMM_33SODIMM_35SODIMM_36SODIMM_38SODIMM_21SODIMM_19SODIMM_140SODIMM_142SODIMM_196SODIMM_194SODIMM_186SODIMM_188SODIMM_138gpio@5d0a0000]  ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpio0|R{R~RSODIMM_23SODIMM_144gpio@5d0b0000]  ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpio0|RR RSODIMM_96SODIMM_75SODIMM_37SODIMM_29SODIMM_43SODIMM_45SODIMM_69SODIMM_71SODIMM_73SODIMM_77SODIMM_89SODIMM_93SODIMM_95SODIMM_99SODIMM_105SODIMM_107SODIMM_98SODIMM_102SODIMM_104SODIMM_106*lvds-tx-on-hoggpio@5d0c0000]  ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpio|RRR R RRRR%SODIMM_129SODIMM_133SODIMM_127SODIMM_131SODIMM_44SODIMM_76SODIMM_31SODIMM_47SODIMM_190SODIMM_192SODIMM_49SODIMM_51SODIMM_53gpio@5d0d0000]  ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpio0|R(R,R 3aSODIMM_57SODIMM_65SODIMM_85SODIMM_135SODIMM_137UNUSABLE_SODIMM_180UNUSABLE_SODIMM_184gpio@5d0e0000] ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0f0000] ,`p 2fsl,imx8qxp-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]fspi_basefspi_mmap ,\} Sfspi_enfspi Edisabledmailbox@5d1b0000] , Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000] ,-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1d0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000]  , Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! , Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d280000]( ,2fsl,imx8qxp-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@r4}Shpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkKclock-controller@5d4100002fsl,imx8qxp-lpcg]Ar4}Shpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkMclock-controller@5d4200002fsl,imx8qxp-lpcg]Br4}Shpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkOclock-controller@5d4300002fsl,imx8qxp-lpcg]Cr4}Shpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkQclock-controller@5d4400002fsl,imx8qxp-lpcg]Dr4}Shpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkclock-controller@5d4500002fsl,imx8qxp-lpcg]Er4}Shpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkclock-controller@5d4600002fsl,imx8qxp-lpcg]Fr4}Shpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkclock-controller@5d4700002fsl,imx8qxp-lpcg]Gr4}Shpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkchosen/bus@5a000000/serial@5a090000gpio-keys 2gpio-keysdefaultTEokaykey-wakeup  * Wake-Upregulator-module-3v32regulator-fixed+V3.32Z2Zregulator-3v32regulator-fixed2Z2Z3.3Vregulator-3v3-vmmc2regulator-fixeddefaultU) <V2Z2Z 3v3_vmmcAd9 interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7i2c0i2c1i2c2i2c3mmc0mmc1mmc2mu0mu1mu2mu3mu4serial0serial1serial2serial3vpu-core0vpu-core1rtc0rtc1device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheclocksoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapstatusmbox-namesmboxes#power-domain-cells#clock-cellspinctrl-namespinctrl-0fsl,pinslinux,keycodestimeout-sec#thermal-sensor-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-namesassigned-clocksassigned-clock-ratespower-domainsslotclock-indices#mbox-cells#dma-cellsdma-channelsdma-channel-maskcs-gpiosdma-namesdmas#pwm-cellstouchscreen-max-pressureadi,resistance-plate-xadi,first-conversion-delayadi,acquisition-timeadi,median-filter-sizeadi,averagingadi,conversion-interval#io-channel-cellsfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsbus-widthnon-removableno-sdno-sdiopinctrl-1pinctrl-2fsl,tuning-start-tapfsl,tuning-stepcd-gpiosvmmc-supplypinctrl-3disable-wpcap-power-off-cardfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetmax-speedreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgpio-hogoutput-highstdout-pathdebounce-intervallabellinux,codewakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpiostartup-delay-us