j8(z ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000 l/vpu@2c000000/vpu-core@2d080000 v/vpu@2c000000/vpu-core@2d090000 /vpu@2c000000/vpu-core@2d0a0000cpus cpu@0cpu2arm,cortex-a53 psci@@,;cpu@1cpu2arm,cortex-a53 psci@@,; cpu@2cpu2arm,cortex-a53 psci@@,; cpu@3cpu2arm,cortex-a53 psci@@,; l2-cache02cacheCO@;l2-cache12cacheCO@opp-table-02operating-points-v2];opp-600000000h#Fo }Iopp-896000000h5goB@}Iopp-1104000000hAʹo}Iopp-1200000000hGo}Iopp-table-12operating-points-v2]opp-600000000h#FoB@}Iopp-1056000000h>HoB@}Iopp-1296000000hM?do}Iopp-1596000000h_!o}Iinterrupt-controller@51a00000 2arm,gic-v3PQQ R RR  ;pmu2arm,armv8-pmuv3 psci 2arm,psci-1.0smctimer2arm,armv8-timer0   system-controller 2fsl,imx-scu tx0rx0gip3$power-controller2fsl,imx8qm-scu-pdfsl,scu-pd; clock-controller2fsl,imx8qm-clkfsl,scu-clk;pinctrl2fsl,imx8qm-iomuxc;Afec1grp              ;5lpuart0grp  ;lpuart2grp  ;lpuart3grp   ;usdhc1grpA!!!!!!!!!A;.usdhc2grpTA!!!!!!;0rtc2fsl,imx8qxp-sc-rtcthermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermal;thermal-zonescpu0-thermal3Atripstrip0Q]passive;trip1Q] criticalcooling-mapsmap0h0m gpu0-thermal3Atripstrip0Q]passivetrip1Q] criticalgpu1-thermal3Atripstrip0Q]passivetrip1Q] criticaldrc0-thermal3A tripstrip0Q]passivetrip1Q] criticalvpu@2c000000 |,,,  disabledmailbox@2d0000002fsl,imx6sx-mu-   disabled; mailbox@2d0200002fsl,imx6sx-mu-   disabled;mailbox@2d0400002fsl,imx6sx-mu-   disabled;vpu-core@2d080000-2nxp,imx8q-vpu-decoder  tx0tx1rx$   disabledvpu-core@2d090000- 2nxp,imx8q-vpu-encoder  tx0tx1rx$ disabledvpu-core@2d0a0000- 2nxp,imx8q-vpu-encoder  tx0tx1rx$ disabledclock-img-ipg 2fixed-clock  img_ipg_clk;bus@58000000 2simple-bus |XXjpegdec@58400000X@ 5peripg   %2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdecjpegenc@58450000XE 1peripg   %2nxp,imx8qm-jpgencnxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgX]0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clk ;clock-controller@585f00002fsl,imx8qxp-lpcgX_0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clk ;clock-dma-ipg 2fixed-clock' dma_ipg_clk; bus@5a000000 2simple-bus |ZZspi@5a0000002fsl,imx7ulp-spiZ  Pperipg 5 5 disabledspi@5a0100002fsl,imx7ulp-spiZ  Qperipg 6 6 disabledspi@5a0200002fsl,imx7ulp-spiZ  Rperipg 7 7 disabledspi@5a0300002fsl,imx7ulp-spiZ  Speripg 8 8 disabledserial@5a060000Z Y ipgbaud 9Ĵ 9 rxtx   okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartdefault(serial@5a070000Z Z ipgbaud :Ĵ : rxtx  disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a080000Z [ ipgbaud ;Ĵ ; rxtx okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartdefault(serial@5a090000Z  \ ipgbaud <Ĵ < rxtx okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartdefault(pwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwmZ ipgper n62 dma-controller@5a1f00002fsl,imx8qm-edmaZ=H @ A B C D E F G H I J K L M N O P Q R S T UUokay;dma-controller@5a9f00002fsl,imx8qm-edmaZ!=H xP l m n o p q r s t uclock-controller@5a4000002fsl,imx8qxp-lpcgZ@5  spi0_lpcg_clkspi0_lpcg_ipg_clk 5;clock-controller@5a4100002fsl,imx8qxp-lpcgZA6  spi1_lpcg_clkspi1_lpcg_ipg_clk 6;clock-controller@5a4200002fsl,imx8qxp-lpcgZB7  spi2_lpcg_clkspi2_lpcg_ipg_clk 7;clock-controller@5a4300002fsl,imx8qxp-lpcgZC8  spi3_lpcg_clkspi3_lpcg_ipg_clk 8;clock-controller@5a4600002fsl,imx8qxp-lpcgZF9 'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk 9;clock-controller@5a4700002fsl,imx8qxp-lpcgZG: 'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk :;clock-controller@5a4800002fsl,imx8qxp-lpcgZH; 'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk ;;clock-controller@5a4900002fsl,imx8qxp-lpcgZI< 'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk <;clock-controller@5a5900002fsl,imx8qxp-lpcgZY (adma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clk ;i2c@5a800000Z@ !!peripg `n6 ` disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z@ ""peripg an6 a disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a820000Z@ ##peripg bn6 b disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ $$peripg cn6 c disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcfZ %%peripg en6 e disabledadc@5a8900002nxp,imx8qxp-adcfZ &&peripg fn6 f disabledcan@5a8d00002fsl,imx8qm-flexcanZ ''ipgper ibZ ix disabledcan@5a8e00002fsl,imx8qm-flexcanZ ((ipgper jbZ jx disabledcan@5a8f00002fsl,imx8qm-flexcanZ ))ipgper kbZ kx disabledclock-controller@5ac000002fsl,imx8qxp-lpcgZ`  i2c0_lpcg_clki2c0_lpcg_ipg_clk `;!clock-controller@5ac100002fsl,imx8qxp-lpcgZa  i2c1_lpcg_clki2c1_lpcg_ipg_clk a;"clock-controller@5ac200002fsl,imx8qxp-lpcgZb  i2c2_lpcg_clki2c2_lpcg_ipg_clk b;#clock-controller@5ac300002fsl,imx8qxp-lpcgZc  i2c3_lpcg_clki2c3_lpcg_ipg_clk c;$clock-controller@5ac800002fsl,imx8qxp-lpcgZe  adc0_lpcg_clkadc0_lpcg_ipg_clk e;%clock-controller@5ac900002fsl,imx8qxp-lpcgZf  adc1_lpcg_clkadc1_lpcg_ipg_clk f;&clock-controller@5acd00002fsl,imx8qxp-lpcgZi  5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clk i;'clock-controller@5a4a00002fsl,imx8qxp-lpcgZJ= 'uart4_lpcg_baud_clkuart4_lpcg_ipg_clk =clock-controller@5ace00002fsl,imx8qxp-lpcgZj  5can1_lpcg_pe_clkcan1_lpcg_ipg_clkcan1_lpcg_chi_clk j;(clock-controller@5acf00002fsl,imx8qxp-lpcgZk  5can2_lpcg_pe_clkcan2_lpcg_ipg_clkcan2_lpcg_chi_clk k;)clock-conn-axi 2fixed-clockCU conn_axi_clk;;clock-conn-ahb 2fixed-clock ! conn_ahb_clk;<clock-conn-ipg 2fixed-clock conn_ipg_clk;:bus@5b000000 2simple-bus |[[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[   *+,  disabledusbmisc@5b0d020082fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ ;+usbphy@5b1000002fsl,imx7ulp-usbphy[,  disabled;*mmc@5b010000 [--- ipgahbper okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcdefault(. mmc@5b020000 [/// ipgahbper -okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcdefault(0=1 I2 R2mmc@5b030000 [333 ipgahbper  disabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0 444 4ipgahbenet_clk_refptp沀sY@[m okay2fsl,imx8qm-fecfsl,imx6sx-fecdefault(5 rgmii-id6mdio ethernet-phy@02ethernet-phy-ieee802.3-c22;6ethernet-phy@12ethernet-phy-ieee802.3-c22ethernet@5b050000[0 777 7ipgahbenet_clk_refptp沀sY@[m  disabled2fsl,imx8qm-fecfsl,imx6sx-fecusb@5b1100002fsl,imx8qm-usb3[ |(88888lpmbusaclkipgcore 沀  disabledusb@5b120000 2cdns,usb3[[[ otgxhcidev0hostperipheralotgwakeup9cdns3,usb3-phy disabledusb-phy@5b1600002nxp,salvo-phy[8salvo_phy_clk  disabled;9clock-controller@5b2000002fsl,imx8qxp-lpcg[ :; 9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk ;-clock-controller@5b2100002fsl,imx8qxp-lpcg[!:; 9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk ;/clock-controller@5b2200002fsl,imx8qxp-lpcg[":; 9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk ;3clock-controller@5b2300002fsl,imx8qxp-lpcg[#0;:: enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clk ;4clock-controller@5b2400002fsl,imx8qxp-lpcg[$0;:: enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clk ;7clock-controller@5b2700002fsl,imx8qxp-lpcg['<:"usboh3_ahb_clkusboh3_phy_ipg_clk ;,clock-controller@5b2800002fsl,imx8qxp-lpcg[(0:::Musb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclk ;8clock-lsio-bus 2fixed-clock lsio_bus_clk;Bbus@5d000000 2simple-bus  |]]pwm@5d0000002fsl,imx27-pwm]ipgper== n62 ^ disabledpwm@5d0100002fsl,imx27-pwm]ipgper>> n62 _ disabledpwm@5d0200002fsl,imx27-pwm]ipgper?? n62 ` disabledpwm@5d0300002fsl,imx27-pwm]ipgper@@ n62 a disabledgpio@5d080000]  2fsl,imx8qm-gpiofsl,imx35-gpio0 AAA$gpio@5d090000]   2fsl,imx8qm-gpiofsl,imx35-gpio@ A(A2 A?AHgpio@5d0a0000]   2fsl,imx8qm-gpiofsl,imx35-gpio0 APAUAh gpio@5d0b0000]   2fsl,imx8qm-gpiofsl,imx35-gpio ArAuAAAAAAAAAAgpio@5d0c0000]   2fsl,imx8qm-gpiofsl,imx35-gpio` AAAA AA;Cgpio@5d0d0000]   2fsl,imx8qm-gpiofsl,imx35-gpio AAA AAAAA;2gpio@5d0e0000]  2fsl,imx8qm-gpiofsl,imx35-gpio  A A  gpio@5d0f0000]  2fsl,imx8qm-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]fspi_basefspi_mmap \ fspi_enfspi  disabledmailbox@5d1b0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000] ,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mu;mailbox@5d1d0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000]    disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000]!   disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000](  2fsl,imx8qm-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@4Bhpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk ;=clock-controller@5d4100002fsl,imx8qxp-lpcg]A4Bhpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk ;>clock-controller@5d4200002fsl,imx8qxp-lpcg]B4Bhpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk ;?clock-controller@5d4300002fsl,imx8qxp-lpcg]C4Bhpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk ;@clock-controller@5d4400002fsl,imx8qxp-lpcg]D4Bhpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk clock-controller@5d4500002fsl,imx8qxp-lpcg]E4Bhpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk clock-controller@5d4600002fsl,imx8qxp-lpcg]F4Bhpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk clock-controller@5d4700002fsl,imx8qxp-lpcg]G4Bhpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk chosen/bus@5a000000/serial@5a060000memory@80000000memory@usdhc2-vmmc2regulator-fixed #SD1_SPWR2-J- bCg;1 interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3vpu-core0vpu-core1vpu-core2device_typeregclocksenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pins#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerangespower-domainsstatus#mbox-cellsclock-frequencyclock-output-namesclock-namesassigned-clocksassigned-clock-ratesslotclock-indicesdma-namesdmaspinctrl-namespinctrl-0#pwm-cells#dma-cellsdma-channelsdma-channel-mask#io-channel-cellsfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-controller#gpio-cellsgpio-rangesstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high