8h(0ti,omap3-ldpti,omap3&!7TI OMAP3430 LDP (Zoom1 Labrador)chosenaliases=/ocp/i2c@48070000B/ocp/i2c@48072000G/ocp/i2c@48060000L/ocp/serial@4806a000T/ocp/serial@4806c000\/ocp/serial@49020000 d/displaymemorymmemoryycpuscpu@0arm,cortex-a8mcpuy}cpu(HАg8 Odp` 'ppmuarm,cortex-a8-pmuyTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocpti,omap3-l3-smxsimple-busyh l3_mainaes@480c5000 ti,omap3-aesaesyH PPABtxrxprm@48306000 ti,omap3-prmyH0`@ clocksvirt_16_8m_ck fixed-clockY  osc_sys_ck ti,mux-clock} y @  sys_ckti,divider-clock} yp) sys_clkout1ti,gate-clock} y pdpll3_x2_ckfixed-factor-clock} @Kdpll3_m2x2_ckfixed-factor-clock} @K dpll4_x2_ckfixed-factor-clock}@Kcorex2_fckfixed-factor-clock}@K wkup_l4_ickfixed-factor-clock}@KB Bcorex2_d3_fckfixed-factor-clock}@Ky ycorex2_d5_fckfixed-factor-clock}@Kz zclockdomainscm@48004000 ti,omap3-cmyH@@clocksdummy_apb_pclk fixed-clockomap_32k_fck fixed-clock2 2virt_12m_ck fixed-clock virt_13m_ck fixed-clock]@ virt_19200000_ck fixed-clock$ virt_26000000_ck fixed-clock virt_38_4m_ck fixed-clockI  dpll4_ckti,omap3-dpll-per-clock}y D 0 dpll4_m2_ckti,divider-clock}?y H) dpll4_m2x2_mul_ckfixed-factor-clock}@K dpll4_m2x2_ckti,gate-clock}y U omap_96m_alwon_fckfixed-factor-clock}@K dpll3_ckti,omap3-dpll-core-clock}y @ 0  dpll3_m3_ckti,divider-clock} y@) dpll3_m3x2_mul_ckfixed-factor-clock}@K dpll3_m3x2_ckti,gate-clock} y U emu_core_alwon_ckfixed-factor-clock}@KV Vsys_altclk fixed-clock  mcbsp_clks fixed-clock9 9dpll3_m2_ckti,divider-clock} y @)  core_ckfixed-factor-clock} @K dpll1_fckti,divider-clock}y @) dpll1_ckti,omap3-dpll-clock}y  $ @ 4 dpll1_x2_ckfixed-factor-clock}@K dpll1_x2m2_ckti,divider-clock}y D). .cm_96m_fckfixed-factor-clock}@K omap_96m_fck ti,mux-clock}y @7 7dpll4_m3_ckti,divider-clock} y@) dpll4_m3x2_mul_ckfixed-factor-clock}@K dpll4_m3x2_ckti,gate-clock}y U omap_54m_fck ti,mux-clock} y @* *cm_96m_d2_fckfixed-factor-clock}@K! !omap_48m_fck ti,mux-clock}! y @" "omap_12m_fckfixed-factor-clock}"@K; ;dpll4_m4_ckti,divider-clock} y@)# #dpll4_m4x2_mul_ckti,fixed-factor-clock}#ky$ $dpll4_m4x2_ckti,gate-clock}$y U} }dpll4_m5_ckti,divider-clock}?y@)% %dpll4_m5x2_mul_ckti,fixed-factor-clock}%ky& &dpll4_m5x2_ckti,gate-clock}&y U^ ^dpll4_m6_ckti,divider-clock}?y@)' 'dpll4_m6x2_mul_ckfixed-factor-clock}'@K( (dpll4_m6x2_ckti,gate-clock}(y U) )emu_per_alwon_ckfixed-factor-clock})@KW Wclkout2_src_gate_ck ti,composite-no-wait-gate-clock}y p+ +clkout2_src_mux_ckti,composite-mux-clock}*y p, ,clkout2_src_ckti,composite-clock}+,- -sys_clkout2ti,divider-clock}-@y pmpu_ckfixed-factor-clock}.@K/ /arm_fckti,divider-clock}/y $emu_mpu_alwon_ckfixed-factor-clock}/@KX Xl3_ickti,divider-clock}y @)0 0l4_ickti,divider-clock}0y @)1 1rm_ickti,divider-clock}1y @)gpt10_gate_fckti,composite-gate-clock} y 3 3gpt10_mux_fckti,composite-mux-clock}2y @4 4gpt10_fckti,composite-clock}34gpt11_gate_fckti,composite-gate-clock} y 5 5gpt11_mux_fckti,composite-mux-clock}2y @6 6gpt11_fckti,composite-clock}56core_96m_fckfixed-factor-clock}7@K8 8mmchs2_fckti,wait-gate-clock}8y  mmchs1_fckti,wait-gate-clock}8y  i2c3_fckti,wait-gate-clock}8y  i2c2_fckti,wait-gate-clock}8y  i2c1_fckti,wait-gate-clock}8y  mcbsp5_gate_fckti,composite-gate-clock}9 y  mcbsp1_gate_fckti,composite-gate-clock}9 y  core_48m_fckfixed-factor-clock}"@K: :mcspi4_fckti,wait-gate-clock}:y  mcspi3_fckti,wait-gate-clock}:y  mcspi2_fckti,wait-gate-clock}:y  mcspi1_fckti,wait-gate-clock}:y  uart2_fckti,wait-gate-clock}:y  uart1_fckti,wait-gate-clock}:y   core_12m_fckfixed-factor-clock};@K< <hdq_fckti,wait-gate-clock}<y  core_l3_ickfixed-factor-clock}0@K= =sdrc_ickti,wait-gate-clock}=y ~ ~gpmc_fckfixed-factor-clock}=@Kcore_l4_ickfixed-factor-clock}1@K> >mmchs2_ickti,omap3-interface-clock}>y  mmchs1_ickti,omap3-interface-clock}>y  hdq_ickti,omap3-interface-clock}>y  mcspi4_ickti,omap3-interface-clock}>y  mcspi3_ickti,omap3-interface-clock}>y  mcspi2_ickti,omap3-interface-clock}>y  mcspi1_ickti,omap3-interface-clock}>y  i2c3_ickti,omap3-interface-clock}>y  i2c2_ickti,omap3-interface-clock}>y  i2c1_ickti,omap3-interface-clock}>y  uart2_ickti,omap3-interface-clock}>y  uart1_ickti,omap3-interface-clock}>y   gpt11_ickti,omap3-interface-clock}>y   gpt10_ickti,omap3-interface-clock}>y   mcbsp5_ickti,omap3-interface-clock}>y   mcbsp1_ickti,omap3-interface-clock}>y   omapctrl_ickti,omap3-interface-clock}>y  dss_tv_fckti,gate-clock}*y dss_96m_fckti,gate-clock}7y dss2_alwon_fckti,gate-clock}y dummy_ck fixed-clockgpt1_gate_fckti,composite-gate-clock}y ? ?gpt1_mux_fckti,composite-mux-clock}2y @@ @gpt1_fckti,composite-clock}?@aes2_ickti,omap3-interface-clock}>y  wkup_32k_fckfixed-factor-clock}2@KA Agpio1_dbckti,gate-clock}Ay  sha12_ickti,omap3-interface-clock}>y  wdt2_fckti,wait-gate-clock}Ay  wdt2_ickti,omap3-interface-clock}By  wdt1_ickti,omap3-interface-clock}By  gpio1_ickti,omap3-interface-clock}By  omap_32ksync_ickti,omap3-interface-clock}By  gpt12_ickti,omap3-interface-clock}By  gpt1_ickti,omap3-interface-clock}By  per_96m_fckfixed-factor-clock}@K per_48m_fckfixed-factor-clock}"@KC Cuart3_fckti,wait-gate-clock}Cy  gpt2_gate_fckti,composite-gate-clock}yD Dgpt2_mux_fckti,composite-mux-clock}2y@E Egpt2_fckti,composite-clock}DEgpt3_gate_fckti,composite-gate-clock}yF Fgpt3_mux_fckti,composite-mux-clock}2y@G Ggpt3_fckti,composite-clock}FGgpt4_gate_fckti,composite-gate-clock}yH Hgpt4_mux_fckti,composite-mux-clock}2y@I Igpt4_fckti,composite-clock}HIgpt5_gate_fckti,composite-gate-clock}yJ Jgpt5_mux_fckti,composite-mux-clock}2y@K Kgpt5_fckti,composite-clock}JKgpt6_gate_fckti,composite-gate-clock}yL Lgpt6_mux_fckti,composite-mux-clock}2y@M Mgpt6_fckti,composite-clock}LMgpt7_gate_fckti,composite-gate-clock}yN Ngpt7_mux_fckti,composite-mux-clock}2y@O Ogpt7_fckti,composite-clock}NOgpt8_gate_fckti,composite-gate-clock} yP Pgpt8_mux_fckti,composite-mux-clock}2y@Q Qgpt8_fckti,composite-clock}PQgpt9_gate_fckti,composite-gate-clock} yR Rgpt9_mux_fckti,composite-mux-clock}2y@S Sgpt9_fckti,composite-clock}RSper_32k_alwon_fckfixed-factor-clock}2@KT Tgpio6_dbckti,gate-clock}Ty gpio5_dbckti,gate-clock}Ty gpio4_dbckti,gate-clock}Ty gpio3_dbckti,gate-clock}Ty gpio2_dbckti,gate-clock}Ty  wdt3_fckti,wait-gate-clock}Ty  per_l4_ickfixed-factor-clock}1@KU Ugpio6_ickti,omap3-interface-clock}Uy gpio5_ickti,omap3-interface-clock}Uy gpio4_ickti,omap3-interface-clock}Uy gpio3_ickti,omap3-interface-clock}Uy gpio2_ickti,omap3-interface-clock}Uy  wdt3_ickti,omap3-interface-clock}Uy  uart3_ickti,omap3-interface-clock}Uy  uart4_ickti,omap3-interface-clock}Uy gpt9_ickti,omap3-interface-clock}Uy  gpt8_ickti,omap3-interface-clock}Uy  gpt7_ickti,omap3-interface-clock}Uy gpt6_ickti,omap3-interface-clock}Uy gpt5_ickti,omap3-interface-clock}Uy gpt4_ickti,omap3-interface-clock}Uy gpt3_ickti,omap3-interface-clock}Uy gpt2_ickti,omap3-interface-clock}Uy mcbsp2_ickti,omap3-interface-clock}Uy mcbsp3_ickti,omap3-interface-clock}Uy mcbsp4_ickti,omap3-interface-clock}Uy mcbsp2_gate_fckti,composite-gate-clock}9y mcbsp3_gate_fckti,composite-gate-clock}9y mcbsp4_gate_fckti,composite-gate-clock}9y emu_src_mux_ck ti,mux-clock}VWXy@Y Yemu_src_ckti,clkdm-gate-clock}YZ Zpclk_fckti,divider-clock}Zy@)pclkx2_fckti,divider-clock}Zy@)atclk_fckti,divider-clock}Zy@)traceclk_src_fck ti,mux-clock}VWXy@[ [traceclk_fckti,divider-clock}[ y@)secure_32k_fck fixed-clock\ \gpt12_fckfixed-factor-clock}\@Kwdt1_fckfixed-factor-clock}\@Ksecurity_l4_ick2fixed-factor-clock}1@K] ]aes1_ickti,omap3-interface-clock}]y rng_ickti,omap3-interface-clock}]y sha11_ickti,omap3-interface-clock}]y des1_ickti,omap3-interface-clock}]y cam_mclkti,gate-clock}^ycam_ick!ti,omap3-no-wait-interface-clock}1y csi2_96m_fckti,gate-clock}8y security_l3_ickfixed-factor-clock}0@K_ _pka_ickti,omap3-interface-clock}_y icr_ickti,omap3-interface-clock}>y des2_ickti,omap3-interface-clock}>y mspro_ickti,omap3-interface-clock}>y mailboxes_ickti,omap3-interface-clock}>y ssi_l4_ickfixed-factor-clock}1@Kf fsr1_fckti,wait-gate-clock}y sr2_fckti,wait-gate-clock}y sr_l4_ickfixed-factor-clock}1@Kdpll2_fckti,divider-clock}y@)` `dpll2_ckti,omap3-dpll-clock}`y$@4a adpll2_m2_ckti,divider-clock}ayD)b biva2_ckti,wait-gate-clock}by modem_fckti,omap3-interface-clock}y  sad2d_ickti,omap3-interface-clock}0y  mad2d_ickti,omap3-interface-clock}0y  mspro_fckti,wait-gate-clock}8y ssi_ssr_gate_fck_3430es2 ti,composite-no-wait-gate-clock}y c cssi_ssr_div_fck_3430es2ti,composite-divider-clock}y @$d dssi_ssr_fck_3430es2ti,composite-clock}cde essi_sst_fck_3430es2fixed-factor-clock}e@K hsotgusb_ick_3430es2"ti,omap3-hsotgusb-interface-clock}=y  ssi_ick_3430es2ti,omap3-ssi-interface-clock}fy  usim_gate_fckti,composite-gate-clock}7 y q qsys_d2_ckfixed-factor-clock}@Kh homap_96m_d2_fckfixed-factor-clock}7@Ki iomap_96m_d4_fckfixed-factor-clock}7@Kj jomap_96m_d8_fckfixed-factor-clock}7@Kk komap_96m_d10_fckfixed-factor-clock}7@K l ldpll5_m2_d4_ckfixed-factor-clock}g@Km mdpll5_m2_d8_ckfixed-factor-clock}g@Kn ndpll5_m2_d16_ckfixed-factor-clock}g@Ko odpll5_m2_d20_ckfixed-factor-clock}g@Kp pusim_mux_fckti,composite-mux-clock(}hijklmnopy @)r rusim_fckti,composite-clock}qrusim_ickti,omap3-interface-clock}By   dpll5_ckti,omap3-dpll-clock}y  $ L 4s sdpll5_m2_ckti,divider-clock}sy P)g gsgx_gate_fckti,composite-gate-clock}y { {core_d3_ckfixed-factor-clock}@Kt tcore_d4_ckfixed-factor-clock}@Ku ucore_d6_ckfixed-factor-clock}@Kv vomap_192m_alwon_fckfixed-factor-clock}@Kw wcore_d2_ckfixed-factor-clock}@Kx xsgx_mux_fckti,composite-mux-clock }tuvwxyzy @| |sgx_fckti,composite-clock}{|sgx_ickti,wait-gate-clock}0y  cpefuse_fckti,gate-clock}y  ts_fckti,gate-clock}2y  usbtll_fckti,wait-gate-clock}gy  usbtll_ickti,omap3-interface-clock}>y  mmchs3_ickti,omap3-interface-clock}>y  mmchs3_fckti,wait-gate-clock}8y  dss1_alwon_fck_3430es2ti,dss-gate-clock}}y dss_ick_3430es2ti,omap3-dss-interface-clock}1y usbhost_120m_fckti,gate-clock}gy usbhost_48m_fckti,dss-gate-clock}"y usbhost_ickti,omap3-dss-interface-clock}1y clockdomainscore_l3_clkdmti,clockdomain}~dpll3_clkdmti,clockdomain} dpll1_clkdmti,clockdomain}per_clkdmti,clockdomainh}emu_clkdmti,clockdomain}Zdpll4_clkdmti,clockdomain}wkup_clkdmti,clockdomain$}dss_clkdmti,clockdomain}core_l4_clkdmti,clockdomain}cam_clkdmti,clockdomain}iva2_clkdmti,clockdomain}dpll2_clkdmti,clockdomain}ad2d_clkdmti,clockdomain }dpll5_clkdmti,clockdomain}ssgx_clkdmti,clockdomain}usbhost_clkdmti,clockdomain }scrm@48002000ti,omap3-scrmyH clocksmcbsp5_mux_fckti,composite-mux-clock}89y mcbsp5_fckti,composite-clock}mcbsp1_mux_fckti,composite-mux-clock}89yt mcbsp1_fckti,composite-clock}mcbsp2_mux_fckti,composite-mux-clock}9yt mcbsp2_fckti,composite-clock}mcbsp3_mux_fckti,composite-mux-clock}9y mcbsp3_fckti,composite-clock}mcbsp4_mux_fckti,composite-mux-clock}9y mcbsp4_fckti,composite-clock}clockdomainscounter@48320000ti,omap-counter32kyH2  counter_32kinterrupt-controller@48200000ti,omap3-intcyH  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ti,tsc20464B@FQZ@clu(& spi@4809a000ti,omap2-mcspiyH Bmcspi2& +,-.tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiyH [mcspi3& tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiyH 0mcspi4&FGtx0rx01w@480b2000 ti,omap3-1wyH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcyH Smmc1=>txrx defaultmmc@480b4000ti,omap3-hsmmcyH @Vmmc2/0txrx disabledmmc@480ad000ti,omap3-hsmmcyH ^mmc3MNtxrx disabledmmu@480bd400ti,omap2-iommuyH mmu_ispmmu@5d000000ti,omap2-iommuy]mmu_iva disabledwdt@48314000 ti,omap3-wdtyH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspyH@mpu ;<  commontxrxmcbsp1 txrx disabledmcbsp@49022000ti,omap3-mcbspyI I mpusidetone>? commontxrxsidetonemcbsp2mcbsp2_sidetone!"txrx disabledmcbsp@49024000ti,omap3-mcbspyI@I mpusidetoneYZ commontxrxsidetonemcbsp3mcbsp3_sidetonetxrx disabledmcbsp@49026000ti,omap3-mcbspyI`mpu 67  commontxrxmcbsp4txrx disabledmcbsp@48096000ti,omap3-mcbspyH `mpu QR  commontxrxmcbsp5txrx disabledsham@480c3000ti,omap3-shamshamyH 0d1Erxsmartreflex@480cb000ti,omap3-smartreflex-coresmartreflex_coreyH smartreflex@480c9000ti,omap3-smartreflex-ivasmartreflex_mpu_ivayH timer@48318000ti,omap3430-timeryH1%timer1*timer@49032000ti,omap3430-timeryI &timer2timer@49034000ti,omap3430-timeryI@'timer3timer@49036000ti,omap3430-timeryI`(timer4timer@49038000ti,omap3430-timeryI)timer59timer@4903a000ti,omap3430-timeryI*timer69timer@4903c000ti,omap3430-timeryI+timer79timer@4903e000ti,omap3430-timeryI,timer8F9timer@49040000ti,omap3430-timeryI-timer9Ftimer@48086000ti,omap3430-timeryH`.timer10Ftimer@48088000ti,omap3430-timeryH/timer11Ftimer@48304000ti,omap3430-timeryH0@_timer12*Susbhstll@48062000 ti,usbhs-tllyH N usb_tll_hsusbhshost@48064000ti,usbhs-hostyH@ usb_host_hsohci@48064400ti,ohci-omap3yHD&Lehci@48064800 ti,ehci-omapyHH&Mgpmc@6e000000ti,omap3430-gpmcgpmcynco ethernet@gpmcsmsc,lan9221smsc,lan9115&(9-GV-dsxKK6HXfs& ynand@0,0 micron,nand ybch8,,"&,d(G6@sRR6(partition@0 X-Loaderypartition@80000U-Bootypartition@1c0000 Environmentypartition@200000Kernely partition@2000000 Filesystemyusb_otg_hs@480ab000ti,omap3-musbyH \] mcdma usb_otg_hs  default2dss@48050000 ti,omap3-dssyHok dss_core}fckdispc@48050400ti,omap3-dispcyH dss_dispc}fckencoder@4804fc00 ti,omap3-dsiyHH@H protophypll disabled dss_dsi1} fcksys_clkencoder@48050800ti,omap3-rfbiyH disabled dss_rfbi}fckickencoder@48050c00ti,omap3-vencyH  disabled dss_venc}fckportendpoint ssi-controller@48058000 ti,omap3-ssissiokyHHsysgddG gdd_mpu }e ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portyHHtxrx&CDssi-port@4805b000ti,omap3-ssi-portyHHtxrx&EFpinmux@480025d8 ti,omap3-padconfpinctrl-singleyH%$4Rregulator-vddvarioregulator-fixed vddvarioA regulator-vdd33aregulator-fixedvdd33aA gpio_keys gpio-keys defaultkey_enterenter "(3key_f1f1 "(;3key_f2f2 "(<3key_f3f3 "(=3key_f4f4 " (>3key_leftleft " (i3key_rightright " (j3key_upup " (g3key_downdown " (l3backlightgpio-backlightC "regulator-lcd-3v3regulator-fixedlcd_3v32Z2ZNpA displaysharp,ls037v7dw01lcd_ l y portendpoint  #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsrangesdmasdma-names#clock-cellsclock-frequencylinux,phandleti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividersinterrupt-controller#interrupt-cells#dma-cellsdma-channelsdma-requestspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvoltti,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xylinux,wakeuppendown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatusti,#tlb-entriesreg-namesinterrupt-namesti,buffer-sizeti,timer-alwonti,timer-dspti,timer-pwmti,timer-securegpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesgpioslinux,codegpio-key,wakeupdefault-onstartup-delay-uspower-supplyenable-gpiosreset-gpiosmode-gpios