=====================================================================
                         ARM-Mץå¸߷ץ
                                  Last Modified: 23 Aug 2008 21:54:54
=====================================================================

ΥɥȤΰ֤Ť

ΥɥȤϡTOPPERS/ASPͥARMvX-Mץå˰ܿ뤿
߷ץǤ롥


ARMVx-MλͤޤȤ

ARMvX-MλͤΤͥ߷פ˴طˤĤƤޤȤ롥

쥸

ѥ쥸R0R1516ढꡤR13Τߤ2Х󥯹PSP,MSPˤȤ
äƤ롥R15PC, R14ϥ󥯥쥸LRˤȤʤäƤ롥R0R3,R12
å쥸Ǥ롥

󥰥٥󥷥

R0R4ʾϥåͤϡR0R1˳Ǽ롥(ARM
구ꤵƤ뤿ᡤѥ˰¸Υ롼Ȥʤ롥)

CONTROL쥸

PSP,MSPڤؤPrivilageUser⡼ɤΥ쥸ѹϡ󥹥
饯Хåեեå̿¹ԤɬפisbˡCONTROL
ξܺ٤ϡARMv7-M Architecture Application Level Reference 
Manual  B1-9 򻲾ȤΤȡ

ߥ٥

٥ơ֥뷿ǡ٥ơ֥Υɥ쥹ϡꥻåȻ0x00ǡ
Vector Table Offset Registerʥޥåץɥ쥸 뤳
ǡǤդΥɥ쥹ֲǽǤ롥

ͥ

ͤͥ٤Ȥʤ롥

ͥ٤Ϻ8bitǤꡤSoC˼Ƥӥåۤʤ롥
ӥåȤ8bitʲξϡLSB̵ˤʤ롥㤨СƤ
ӥå7bitξϡӥå0̵Ȥʤ롥

ͥ٤ΥӥåȥեɤLSBӥåȤ򥵥ͥ٤ȸƤ֥ե
ꤹ뤳ȤǽǤ롥Ĥξ̥ӥåȤץꥨץͥ٤
Ƥ֡ץꥨץͥ٤Ʊǡͥ٤ۤʤͥ٤Υ롼
פϡߤץꥨץȤ뤳ȤǤʤ

Reset,NMI,Hard Fault ʳ㳰ϳߤƱͤͥ٤ǽǤꡤ
ߥޥǽˤꡤȯػߤ뤳ȤǽǤ롥

CPU⡼

ץåϡThread⡼ɤ⤷Handler⡼ɤΤ줫Υ⡼ɤȤ
롥

ꥻåȻξ

ꥻåȻThread⡼ɡMSPͭȤʤäƤ롥

Handler⡼

㳰/ߤդܤ⡼ɡդ㳰/ߤ㳰
椬IPSR˥åȤ롥㳰ֹϡTRMƤֹǤ롥

        㳰              㳰ֹ
  Reset                      1
  Non-makable Interrupt      2
  Hard Fault                 3
  Memory Management          4
  Bus Fault                  5
  Usage Fault                6
  SVCall                    11
  Debug Monitor             12
  PendSV                    14
  SysTick                   15
  IRQ0                      16
  IRQ1                      17
  ..

㳰/ߤդȡդ㳰/ߤٰͥʲ㳰/
ߤػߤ롥ͥ٥ޥ"NVICͥ٥ޥ"ȸƤ֡ͥ
ϡեȥѹ뤳ȤǤ㳰/ߤΥ꥿ˤ
ͤ˼ưŪ롥

åݥ󥿡PSPMSP

åݥ󥿤ϡPSPMSPꡤ¾Ū˻ѲǽǤ롥Handler
ɤǤMSPΤ߻ѲǽǤꡤThread⡼ɤǤCONTROL쥸
ǽǤ롥CONTROL쥸1ӥåܤ򥻥åȤPSPͭˡꥢ
ȡMSPͭˤʤ롥

Thread⡼ɤHandler⡼ɤ

Thread⡼ɤHandler⡼ɤؤܤϡ㳰/ߤդ뤳Ȥ
ȯ롥Handler⡼ɤThread⡼ɤؤܤϡPC
EXC_RETURN(0xfffffffx)ͤꤹ뤳ȤˤԤ㳰꥿
Ƥ֡ˡEXC_RETURNβ4bitˤꡤΥ⡼ɤѤ륹å
󥿤ѹǽǤ롥㳰꥿ˤꡤPRIMASKBASEPRIͤѲ
ʤFAULTMASKͤ'0'˥ꥢ롥

EXC_RETURN

㳰/߼դlrꤵ͡ӥå314ӥåȤ'1'ǡ
4bitϡդCPU⡼ɤ䥹åȿǤͤȤʤäƤ롥

 0b0001 : Handler⡼
 0b1001 : Thread⡼ with MSP
 0b1101 : Thread⡼ with PSP

Thread⡼ɤHandler⡼ɤȽ

Υ⡼ɤȽꤹˤϡIPSR򸫤ơ'0'ʤThread⡼ɡʳ
ʤ顤Handler⡼ɤȤʤ롥

BASEPRI쥸

ꤷٰͥʲͥ٤γߤμդػߤ롥ͥ٥ޥ
"BASEPRIͥ٥ޥ"ȸƤ֡'0'ꤹȡƤγߤĤ롥
㳰/ߤμդȥ꥿ˤѲʤ㳰/ߤФ
ͥ٥ޥϡNVICͥ٥ޥBASEPRIͤι⤤ͤ
ˤȤʤ롥

FAULTMASK

FAULTMASK'1'򥻥åȤ뤳ȤˤꡤNMIʳƤγߤػߤ롥
FAULTMASKϡ㳰Υ꥿ˤ'0'˥ꥢ롥

PRIMASKWFI

PRIMASK'1'ꤹȡNMI  Hardware Fault ʳ㳰/ߤ
ߤ롥PRIMASKϳߤεĤȳԤ򥢥ȥߥå˹ԤѤ
롥ŪˤϡPRIMASKåȤƤ֤wfi¹Ԥȡ
ԤȤʤꡤ߼դȥϥɥ¹Ԥˡwfi꥿
Ƥ롥

㳰/ߤμ

㳰/ߤդȡդ˥ƥ֤ʥå˰ʲΥ
  ƥȤ¸(㳰ե졼ȸƤ)

   -----------
  |    R0     |  <- new SP
   -----------
  |    R1     |
   -----------
  |    R2     |
   -----------
  |    R3     |
   -----------
  |    R12    |
   -----------
  |    LR     |
   -----------
  |    PC     |
   -----------
  |   xPSR    |
   -----------
  |           | <- old SP

ץåHandler⡼ɤȤ롥MSPͭȤʤ롥
դ㳰/ߤ㳰ֹIPSRꤹ롥
NVICͥ٥ޥդ㳰/ߤͥ٤ꤹ롥
lrEXC_RETURNͤꤵ롥
٥ơ֥ɤ߹ߥϥɥ¹Ԥ롥

㳰/ߤΥ꥿

pcEXC_RETURNͤꤹ뤳Ȥˤꡤ㳰/ߤ꥿󤹤롥
pcؤ˻Ѳǽ̿ˤ¤ꡤʲ̿᤬ѲǽǤ롥

  POP/LDM, LDR, BX

̤

٥ơ֥ϿؿΥɥ쥹LSB'1'ˤ٤?
NVIC㳰ߤΥͥȲŪ˴Ƥ餷
  (!ե󥹤餫)
    եȥǤϡͥȤĢ碌С꥿󥹥å¤
    Ƥʤ


OSμ

1.å̾

 1-1 cm3(Cortex-M3)
 1-2 armv7m(ARMV7M)
 1-3 arm_m

cm3ǤϡCoretex-M1(armv6-m)򥵥ݡȤȤʤ롥armv7mǤϡ
armv8m꡼줿Ȥʤ롥ARM¸JSPǤϡarmv4Ȥ
äƤarmv5armv7ư뤿ASPǤñarmȤΤᡤ
arm_m̵ȹͤ롥


2.Thread⡼ɤHandler⡼ɤλȤʬ

 2-1
  ƥȤThread⡼ɡ󥿥ƥȤHandler⡼
  ɤư롥

 2-2
  ƥȤ󥿥ƥȶHandler⡼ɤư
  롥

ץå߷ˤθ2-1ͭϡ2-1ǤȤƤϡ
ߥϥɥ餫饿ؤΥ꥿˥⡼ɤѹʲͤ¿ȯ뤳
Ȥ󤲤롥

1.ߥϥɥ               : Handler⡼
2.㳰ϥɥθƤӽФ : Thread⡼
3.ؤΥ꥿       : Handler⡼
4.κƳ                 : Thread⡼

3Handler⡼ɤ˰ܹԤɬפΤϡ㳰ե졼Ѥ
ˤϡHandler⡼ɤ㳰꥿Ԥɬפ뤿Ǥ롥ARM
ϡʣ쥸ΥɤCPSRƱ˹Ԥ뤬M3ϹԤʤᡤ
ˡǳΥ˥꥿󤹤ɬפ롥

2-2ξγߥϥɥ餫饿ؤΥ꥿˥⡼ɤѹʲ
˼ޤ2-2Ǥϳͥ٤κͤ򥿥μ¹Իͥ٤Ȥ
ƥꥶ֤ɬפ롥

1.ߥϥɥ               : Handler⡼
2.NVICͥ٥ޥ'0'0     : Thread⡼
3.ͥ٤Handler⡼ɤ  : Handler⡼
4.㳰ϥɥθƤӽФ : Handler⡼
5.ؤΥ꥿   : Thread⡼
3.ؤΥ꥿           : Handler⡼
4.κƳ                 : Handler⡼

ߥϥɥ餫饿Υ꥿˴ؤƤϡ2-2ǤäƤ⡤2¹Ԥ
ˡNVICͥ٥ޥ'0'ˤ뤿ᡤ㳰꥿Ԥɬ
롥ޤNVICΤߤΥͥȲƤ뤿ᡤ34
ؤܤΤˡä㳰/ߤդ֤ˤɬפ뤿
ᡤŪ2-1ʾܤɬפȤʤ롥

2-2ξϡMSPȤʤᡤߤǥͥȲȽǤơ
åؤɬפ롥

HRPǥݸѤ2-1Ȥʤ롥

ʾͳˤꡤ2-1Ѥ롥2-1ϡͥ뵯ưIDLE롼
פΰƤɬפ롥ˤĤƤӵ롥


3.ǥѥåμ¹ԥ⡼

 3-1
  Thread⡼ɤǼ¹Ԥ

 3-2
  Handler⡼ɤǼ¹Ԥ

ǥѥåThread⡼ɤǼ¹ԤȡߤˤץꥨץȤ
ϼΤ褦ʥѥˤʤ롥

 1. ǥѥåƤӽФ : Thread⡼ 
 2. ǥѥå¹     : Thread⡼
 3. 㳰¹         : Thread⡼
 4ؤΥ꥿ : Handler⡼
 5. κƳ           : Thread⡼

ߥϥɥ餫鼫ǥѥåإ꥿󤹤ϼΥ
ˤʤ롥

 1.ߥϥɥ               : Handler⡼
 2.ǥѥå¹           : Thread⡼
 3.㳰ϥɥθƤӽФ : Thread⡼
 4.ؤΥ꥿           : Handler⡼
 5.κƳ                 : Thread⡼

ǥѥåHandler⡼ɤǼ¹Ԥȡߤˤץꥨ
ץȤ줿ϼΤ褦ʥѥˤʤ롥

 1. ǥѥåƤӽФ : Thread⡼ 
 2. ǥѥå¹     : Handler⡼
 3. 㳰¹         : Thread⡼
 4ؤΥ꥿     : Handler⡼
 5. κƳ           : Thread⡼

ߥϥɥνи鼫ǥѥåإ꥿󤹤
Υѥˤʤ롥

 1.ߥϥɥ               : Handler⡼
 2.ǥѥå¹           : Handler⡼
 3.㳰ϥɥθƤӽФ : Thread⡼
 4.ؤΥ꥿           : Handler⡼
 5.κƳ                 : Thread⡼

㳰ϥɥ餬ʤOSξϡHandler⡼ɤǼ¹Ԥ⡼
ܤβ뤬㳰ϥɥ餬ȡThread⡼ɤ
ܲ뤿ᡤThread⡼ɤȤ롥

ݸθȡǥѥåHandler⡼ɤư
Ψ褤ȹͤSVCǥϥɥƤӽФHandler⡼ɤȤʤ뤿
ˡ


4.åλȤʬ

 4-1
  ƥȤPSP, 󥿥ƥȤMSP
 4-2
  ƥȡ󥿥ƥȶMSP

4-2ξ硤ߤǥͥȲȽǤơåؤ
ɬפ롥2ǥƥȤThread⡼ɡ󥿥ƥ
Handler⡼ɤưȤᡤ4-1Ѥȡߤ
ǼưŪ˥åڤؤ롥Thread⡼ɤǤPSPΥ⡤
mrs/msr̿ǹԤ뤿ᡤ4-1Ѥ롥


5.ƥȤȽ

 5-1
  IPSR'0'(Thread⡼)ʤ饿ƥȡ'1'(Handler⡼
  )ʤ󥿥ƥȤȤ롥

 5-2
  ߤΥͥȲݻѿѰա1ʾ󥿥ƥȡ

 5-3
  ƥ֤ʥåˤȽǡMSPʤ󥿥ƥȡPSPʤ
  ƥȤȤ

5-1ϡեȥ¦ǥƥȴΤνԤɬפʤ
åȤ롥ʤ顤ͥεưThread⡼ɤǤ뤿
ᡤHandler⡼ɤذܹԤɬפ롥ASPͥǤϡIDLE롼׼¹
󥿥ƥȤȤưɬפ뤿ᡤIDLE롼פ
Handler⡼ɤưɬפ롥IDLE롼פϥǥѥå㤫
ӽФ롥3᤿褦ˡǥѥåThread⡼ɤư
ᡤIDLE롼פƤӽФݤˤϡHandler⡼ɤܤɬפ롥
Handler⡼ɤؤܤϡSVC/PendSVCѤȼ¸ǽǤ뤬6γ
ߤ˥ץꥨץȤ줿ؤΥ꥿Handler⡼ɤؤΰܹԤ
SVC/PendSVCλѤɬפȤʤ뤿ᡤSVCϥɥǤϡɤŪǸƤӽ
줿ȽꤹɬפФƤ뤿ᡤХإåɤ礹롥

5-2Ǥϡͥ뵯ưIDLE롼׻ѿ'1'ꤹФ褤Ȥ
ʤ롥ξ硤ͥ뵯ưIDLE롼׻Thread⡼ɤǼ¹ԤƤ
ư꤬ʤ褦ä˳ߤν߷פդɬפ롥

ͥ뵯ư˴ؤƤϡߤػߤƤꡤߤʤΤ
äϤʤIDLE롼׻ϡThread⡼ɤMSPPSP򤬲ǽǤ
뤳ȤѤơ󥿥ƥȤΥåǤMSPѹ롥
㳰/ߤǤϡ¿ųߤǤ뤫EXC_RETURNΥ⡼Ƚ
ӥåȤǤϤʤåȽӥåȤǹԤʤ㳰/ߤ
Υ꥿˴ؤƤϡ¿ųߤȽϡƱͤEXC_RETURNΥ
åȽӥåȤǹԤФ褤㳰꥿pc
EXC_RETURNͤΧ0xfffffffd (Thread⡼ with MSP)ȤΤǤϤʤ
㳰/߼դLRꤵEXC_RETURNѤ뤳ȤˤꡤIDLE
롼פ˳Ǥʤ꥿󤹤롥

ͥ뵯ưϡMSPƥ֤Ǥꡤߥϥɥ¹ԻHandler
⡼ɤǤ뤳ȤMSPƥ֤ǤꡤIDLE롼׻MSP򥢥ƥ
ꤹȡ󥿥ƥȤơMSP򥢥ƥ֤ˤư
뤳Ȥˤʤ롥ޤ߻ϳ˥ƥ֤ʥåξ󤬡
EXC_RETURNꤵ롥ΤᡤƥȤȽϡߥͥȲ
ݻѿʤȤ⡤ƥ֤ʥå򸫤Ф褤Ȥˤʤ롥
ޤexc_sense_context()˴ؤƤϡ㳰ե졼EXC_RETURNɲ
ƤˤȽǤФ褤ʾͳˤꡤ5-3Ѥ롥


6.ߤ˥ץꥨץȤ줿ؤΥ꥿Handler⡼ɤؤΰ
  ˡ

 6-1
  SVCѤ
 6-2
  PendSVCѤ

PendSVCSVCΰ㤤ϡPendSVC׵᤬塼󥰤졤SVC׵᤬
󥰤ʤȤǤ롥ߤ˥ץꥨץȤ줿ؤΥ꥿
Handler⡼ɤؤΰܹԤϡ塼󥰤줺¨¤˽ɬ
פ뤿ᡤɤǼ¸Ƥʤɤ򥫡ͥΥ꥽
ƻѤ뤫Ǥ롥

ɤȤȤƤ⡤ͥ٤꤬Ȥʤ롥ǥѥå㤫
ߤ˥ץꥨץȤ줿ؤΥ꥿ޤǤνϡʤȤCPU
å֤Ǽ¹ԤʤФʤʤSVCPendSVCϤɤͥ
ĤᡤNVICͥ٥ޥBASEPRIͥ٥ޥ⤤硤
ʤ

CPUå֤BASEPRIǼ¸硤ͤSVCPendSVC
ꤷͤ㤯ɬפ롥ȡSVCPendSVCͥ٤
CPUåͥ٥ޥͤ⤤͡¾γߤ⤤ͥ١ˤ
ɬפ롥

CPUå֤FAULTMASKPRIMASKǼ¸ϡ餬ꤵ
ȡSVCPendSVCդʤᡤäBASEPRIˤߤ
褦ꤹɬפ롥ξ⡤SVCPendSVC¾γ
⤤ͥ٤ꤹɬפ롥

ʾˤꡤHandler⡼ɤؤΰܹԤΤˤϡCPUå֤BASEPRI
¸SVCPendSVCꤹͥ٤򥫡ͥκǹͥ٤
Ĺ⤤ͥ٤ꤹɬפ롥


7. 㳰/߽Ǥ¿ųߤȽ

7-1
 EXC_RETURNΥ⡼Ƚӥå
7-2
 EXC_RETURNΥåȽӥå
7-3
 ߥͥȲδѿ

㳰/߼դϡդ㳰/߰ʲγߤ϶ػߤ뤬
߶ػ߾֤ˤϤʤʤΤᡤߥͥȲδѿ򥤥
Ȥ˳ߤǽ뤿ᡤ7-3ϻѤ뤳Ȥ
ʤ

5ǵ̤ꡤIDLE롼פThread⡼ɤǼ¹Ԥ뤿ᡤ7-1ǤϤʤ
7-2ȽǤɬפ롥


8. IDLE롼

8-1
 Thread⡼ɤǼ¹
8-2
 Handler⡼ɤǼ¹

5ǵ̤ꡤThread⡼ɤǼ¹ԤǤХإåɤ
Thread⡼ɤǼ¹ԤƤ⡤ߤν󥿥
ȤȽǤСThread⡼ɤʤ


9ͥγߤΥݡ

9-1
 ͥγߤ򥵥ݡȤʤ
9-2
 ͥγߤ򥵥ݡȤ

٥ơ֥򥵥ݡȤƤꡤߥϥɥCǵҲǽǤ
뤿ᡤݡȤưפǤ뤿ᡤݡȤ롥


10. CPUå

10-1
 BASEPRI 
10-2 
 FAULTMASK/PRIMASK

ͥδγߤ򥵥ݡȤʤ顤BASEPRIѤɬפ
롥


11. ߥåCPU㳰δط

11-1
 BASEPRI 
11-2 
 FAULTMASK/PRIMASK 

FAULTMASK/PRIMASKѤȡNMI  Hardware Fault ʳCPU㳰
ߤƤޤ

BASEPRIѤȡߥåˤCPU㳰դϡ
BASEPRIѤơǹͥ٤CPU㳰Τ˥ꥶ֤ɬפ롥

ߥå⡤CPU㳰դ褦ˤBASEPRIѤɬ
פ롥

IRON4.0ͤ3.5.3ǤϡCPU㳰ͥ٤ϼΤ褦Ƥ롥

"CPU㳰ϥɥ̤ͥϡCPU㳰ȯͥ٤ȡǥ
ѥå̤ͥΤ줫⤤"

CPU㳰ȯͥ٤⤤ȤΤǡCPUåߥ
å֤ΥȯǤ⡤ͥ褷Ƽ¹Ԥ٤Ȥͤ
롥

TOPPERSɸ߽ǥλͽǤϡCPU㳰ϡץå
˰ۤʤ뤿ᡤCPU㳰νǥɸಽƤоݳȤƤ롥
ᡤARM-MǤΰơޥ˥奢Ф褤ȹͤ롥


12. ͥ٤ͥ٤Ѵ

ͥ٤ȤAPIǻꤹͥ(PRI)ΤȤǤꡤͤ
ۤͥ٤⤤ߥϥɥˤϡ-1Ϣ³ͤǽ
롥ͥ٤ϡBASEPRINVICͥ٥쥸ꤹͤǤ롥

ͥ٤Υӥå TBITW_IPRI Ȥȡǽʳ
ͥ٤ϼΤ褦ˤʤ롥

  TIPM_ENAALLʡ0ˡ -(1 << TBITW_IPRI)


13. ͥκǹͥ(CPUå֤Ǥͥ٥ޥ)

6.ǽҤ٤褦ˡߤνиSVCϥɥƤӽФɬפ뤿ᡤ
SVCϥɥCPUå֤BASEPRIꤹͥ٥ޥ⤤ͥ
ꤹɬפ롥

ͥ٤Υӥå TBITW_IPRIͥΥͥ٤
ӥåTBIT_IPRIȤȡCPUå֡ʥͥߤ
ǽʺǹͥ١ˤȤƻǽͥ٥ޥϰϤϰʲͤ
ϤȤʤ롥

    -(2^(TBIW_IPRI)) + (2^TBITW_SUBIPRI))  -1


14. ̤

ߥåCPU㳰δط
  BASEPRIȤäȤƤ⡤CPU㳰¾㳰ȯȡ
  㳰ϼդʤᡤITRONͤʤ
  ->ƥޥ˥奢뵭ܤƨ뤫.
  ץƥ㳰ޥǽǤ뤿׷


ʾ塥
