8p(e8khadas,edge2rockchip,rk3588s + 7Khadas Edge2aliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55 psci+ 2 B0,W gt@@ cpu@100cpuarm,cortex-a55 psci+ W gt@@ cpu@200cpuarm,cortex-a55 psci+ W gt@@cpu@300cpuarm,cortex-a55 psci+ W gt@@cpu@400cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@500cpuarm,cortex-a76 psci+ W gt@@cpu@600cpuarm,cortex-a76 psci+ 2 B0,W gt@@cpu@700cpuarm,cortex-a76 psci+ W gt@@ idle-statespscicpu-sleeparm,idle-state6dGxW l2-cache-l0cacheiv@ht l2-cache-l1cacheiv@ht l2-cache-l2cacheiv@htl2-cache-l3cacheiv@htl2-cache-b0cacheiv@htl2-cache-b1cacheiv@htl2-cache-b2cacheiv@htl2-cache-b3cacheiv@htl3-cachecachei0v@htfirmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci+usb disabledusb@fc840000"rockchip,rk3588-ohcigeneric-ohci+usb disabledusb@fc880000"rockchip,rk3588-ehcigeneric-ehci+usb disabledusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci+usb disabledusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(+jihkr&ref_clksuspend_clkbus_clkutmipipe(host usb3-phy 0utmi_wide94@Xy disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXasyscon@fd58c000rockchip,rk3588-sys-grfsysconX#syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ $syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ%syscon@fd5b0000rockchip,rk3588-php-grfsyscon[ syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phy9ophyapb+phyclk usb480m_phy2 disabledhost-port disabledsyscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phy9p phyapb+phyclk usb480m_phy3 disabledhost-port disabledsyscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|2]q@BA.2Fq)׫ׄe/ׄ eZ р  i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=+ts i2cpclk!default+ disabledvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8+]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop"##$4%E& disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~+]\ aclkifaceR disabled"serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK+baudclkapb_pclk_''dtxrx(defaultnx disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclk)default disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ pwmpclk*default disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm + pwmpclk+default disabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ pwmpclk,default disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd&power-controller!rockchip,rk3588-power-controller+okaypower-domain@8+power-domain@9  +!#" -./+power-domain@10 +!#"0power-domain@11 +!#"1power-domain@12 +2345power-domain@13 +power-domain@14(+6power-domain@15 +7power-domain@16+ 89:+power-domain@17 + ;<=power-domain@21+ >?@ABCDE+power-domain@23+CAFpower-domain@14 +6power-domain@15+7power-domain@22+Gpower-domain@24+[Z]HI+power-domain@258+ZJpower-domain@268+QKLpower-domain@270+MNOP+power-domain@28 +QRpower-domain@29(+STpower-domain@30+z{Upower-domain@31@+WVWXYpower-domain@33!+WZ[power-domain@34"+WZ[power-domain@37%+2Zpower-domain@38&+45power-domain@40([i2s@fddc0000rockchip,rk3588-i2s-tdm+mclk_txmclk_rxhclk2_\dtx9tx-m disabledi2s@fddf0000rockchip,rk3588-i2s-tdm+445mclk_txmclk_rxhclk21_\dtx9tx-m disabledi2s@fddfc000rockchip,rk3588-i2s-tdm+00,mclk_txmclk_rxhclk2-_\drx9rx-m disabledqos@fdf35000rockchip,rk3588-qossysconP 2qos@fdf35200rockchip,rk3588-qossysconR 3qos@fdf35400rockchip,rk3588-qossysconT 4qos@fdf35600rockchip,rk3588-qossysconV 5qos@fdf36000rockchip,rk3588-qossyscon` Uqos@fdf39000rockchip,rk3588-qossyscon Zqos@fdf3d800rockchip,rk3588-qossyscon [qos@fdf3e000rockchip,rk3588-qossyscon Wqos@fdf3e200rockchip,rk3588-qossyscon Vqos@fdf3e400rockchip,rk3588-qossyscon Xqos@fdf3e600rockchip,rk3588-qossyscon Yqos@fdf40000rockchip,rk3588-qossyscon Sqos@fdf40200rockchip,rk3588-qossyscon Tqos@fdf40400rockchip,rk3588-qossyscon Mqos@fdf40500rockchip,rk3588-qossyscon Nqos@fdf40600rockchip,rk3588-qossyscon Oqos@fdf40800rockchip,rk3588-qossyscon Pqos@fdf41000rockchip,rk3588-qossyscon Qqos@fdf41100rockchip,rk3588-qossyscon Rqos@fdf60000rockchip,rk3588-qossyscon 8qos@fdf60200rockchip,rk3588-qossyscon 9qos@fdf60400rockchip,rk3588-qossyscon :qos@fdf61000rockchip,rk3588-qossyscon ;qos@fdf61200rockchip,rk3588-qossyscon <qos@fdf61400rockchip,rk3588-qossyscon =qos@fdf62000rockchip,rk3588-qossyscon 6qos@fdf63000rockchip,rk3588-qossyscon0 7qos@fdf64000rockchip,rk3588-qossyscon@ Fqos@fdf66000rockchip,rk3588-qossyscon` >qos@fdf66200rockchip,rk3588-qossysconb ?qos@fdf66400rockchip,rk3588-qossyscond @qos@fdf66600rockchip,rk3588-qossysconf Aqos@fdf66800rockchip,rk3588-qossysconh Bqos@fdf66a00rockchip,rk3588-qossysconj Cqos@fdf66c00rockchip,rk3588-qossysconl Dqos@fdf66e00rockchip,rk3588-qossysconn Eqos@fdf67000rockchip,rk3588-qossysconp Gqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 0qos@fdf71000rockchip,rk3588-qossyscon 1qos@fdf72000rockchip,rk3588-qossyscon -qos@fdf72200rockchip,rk3588-qossyscon" .qos@fdf72400rockchip,rk3588-qossyscon$ /qos@fdf80000rockchip,rk3588-qossyscon Jqos@fdf81000rockchip,rk3588-qossyscon Kqos@fdf81200rockchip,rk3588-qossyscon Lqos@fdf82000rockchip,rk3588-qossyscon Hqos@fdf82200rockchip,rk3588-qossyscon" Ipcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0+CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`]]]] /0^07 pcie-phy"T @ @0 @@dbiapbconfig9). pwrpipe+ disabledlegacy-interrupt-controllerA ]pcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0+DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`____ /@^@7` pcie-phy"T @ @0 A@dbiapbconfig9*/ pwrpipe+ disabledlegacy-interrupt-controllerA _dfi@fe060000rockchip,rk3588-dfi@&0:Eaethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(+67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref!9$ stmmaceth#V gbwcd disabledmdiosnps,dwmac-mdio+stmmac-axi-configbrx-queues-configcqueue0queue1tx-queues-configdqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(+b_eTosatapmaliverxoobrefasic + disabledsata-port@0@` sata-phy, ; sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(+dagVqsatapmaliverxoobrefasic + disabledsata-port@0@ sata-phy, ; spi@fe2b0000 rockchip,sfc+@+/0clk_sfchclk_sfc+ disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ +  biuciuciu-driveciu-sampleJU defaultefgh( disabledmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ +biuciuciu-driveciu-sampleJU defaulti% disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.2-., B n6 (+,*+-.corebusaxiblocktimerU jklmndefault(9corebusaxiblocktimerokaycmu{i2s@fe470000rockchip,rk3588-i2s-tdmG++/(mclk_txmclk_rxhclk2)-_''dtxrx&9*+ tx-mrx-mdefault(opqrstuvwx disabledi2s@fe480000rockchip,rk3588-i2s-tdmH+y}umclk_txmclk_rxhclk_''dtxrx9^_ tx-mrx-mdefault(yz{|}~ disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI+i2s_clki2s_hclk2_dtxrx&default disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ+%i2s_clki2s_hclk2"_dtxrx&default disabledinterrupt-controller@fe600000 arm,gic-v3 `h Aa8+msi-controller@fe640000arm,gic-v3-itsd^msi-controller@fe660000arm,gic-v3-itsfppi-partitionsinterrupt-partition-0interrupt-partition-1 dma-controller@fea10000arm,pl330arm,primecell@ VW+n apb_pclk'dma-controller@fea30000arm,pl330arm,primecell@ XY+o apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c+{ i2cpclk>default+ disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c+| i2cpclk?default+ disabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c+} i2cpclk@default+ disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c+~ i2cpclkAdefault+ disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkBdefault+ disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !+TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt+dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF+spiclkapb_pclk_''dtxrx' default+ disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG+spiclkapb_pclk_''dtxrx' default+ disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH+spiclkapb_pclk_dtxrx' default+ disabledspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI+spiclkapb_pclk_dtxrx' default+ disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL+baudclkapb_pclk_'' dtxrxdefaultxn disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM+baudclkapb_pclk_' ' dtxrxdefaultxnokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN+baudclkapb_pclk_' ' dtxrxdefaultxn disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO+baudclkapb_pclk_ dtxrxdefaultxn disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP+baudclkapb_pclk_ dtxrxdefaultxn disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ+baudclkapb_pclk_ dtxrxdefaultxn disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR+baudclkapb_pclk_\\dtxrxdefaultxn disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS+baudclkapb_pclk_\ \ dtxrxdefaultxn disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT+baudclkapb_pclk_\ \ dtxrxdefaultxn disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkdefault disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+LK pwmpclkdefault disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +LK pwmpclkdefault disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+LK pwmpclkdefault disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkdefault disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+ON pwmpclkdefault disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +ON pwmpclkdefault disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+ON pwmpclkdefault disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkdefault disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm+RQ pwmpclkdefault disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm +RQ pwmpclkdefault disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0+RQ pwmpclkdefault disabledtsadc@fec00000rockchip,rk3588-tsadc+tsadcapb_pclk2B9VWtsadc-apbtsadc.E\w gpiootpout disabledadc@fec10000rockchip,rk3588-saradc+saradcapb_pclk9U saradc-apb disabledi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkCdefault+ disabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkDdefault+ disabledi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c+ i2cpclkEdefault+ disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ+spiclkapb_pclk_\ \dtxrx' default+ disabledefuse@fecc0000rockchip,rk3588-otp +otpapb_pclkphyarb9 otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1cnpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[+p apb_pclk\phy@fee00000rockchip,rk3588-naneng-combphy+vW refapbpipe2B9<Cphyapb  disabled`phy@fee20000rockchip,rk3588-naneng-combphy+xW refapbpipe2B9>Ephyapb  disabledsram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank+qr Agpio@fec20000rockchip,gpio-bank+st Agpio@fec30000rockchip,gpio-bank+uv@ Agpio@fec40000rockchip,gpio-bank+wx` Agpio@fec50000rockchip,gpio-bank+yz Apcfg-pull-uppcfg-pull-down pcfg-pull-nonepcfg-pull-none-drv-level-2'pcfg-pull-up-drv-level-1'pcfg-pull-up-drv-level-2'pcfg-pull-none-smt6auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnoutKjemmc-bus8Kkemmc-clkKlemmc-cmdKmemmc-data-strobeKneth1fspigmac1gpuhdmii2c0i2c0m0-xfer K !i2c1i2c1m0-xfer K  i2c2i2c2m0-xfer K  i2c3i2c3m0-xfer K  i2c4i2c4m0-xfer K  i2c5i2c5m0-xfer K  i2c6i2c6m0-xfer K  i2c7i2c7m0-xfer K  i2c8i2c8m0-xfer K  i2s0i2s0-lrckKoi2s0-sclkKpi2s0-sdi0Kqi2s0-sdi1Kri2s0-sdi2Ksi2s0-sdi3Kti2s0-sdo0Kui2s0-sdo1Kvi2s0-sdo2Kwi2s0-sdo3Kxi2s1i2s1m0-lrckKyi2s1m0-sclkKzi2s1m0-sdi0K{i2s1m0-sdi1K|i2s1m0-sdi2K}i2s1m0-sdi3K~i2s1m0-sdo0K i2s1m0-sdo1K i2s1m0-sdo2K i2s1m0-sdo3K i2s2i2s2m1-lrckKi2s2m1-sclkK i2s2m1-sdiK i2s2m1-sdoK i2s3i2s3-lrckKi2s3-sclkKi2s3-sdiKi2s3-sdoKjtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmupwm0pwm0m0-pinsK)pwm1pwm1m0-pinsK*pwm2pwm2m0-pinsK+pwm3pwm3m0-pinsK,pwm4pwm4m0-pinsK pwm5pwm5m0-pinsK pwm6pwm6m0-pinsK pwm7pwm7m0-pinsK pwm8pwm8m0-pinsK pwm9pwm9m0-pinsK pwm10pwm10m0-pinsK pwm11pwm11m0-pinsK pwm12pwm12m0-pinsK pwm13pwm13m0-pinsK pwm14pwm14m0-pinsK pwm15pwm15m0-pinsK refclksatasata0sata1sata2sdiosdiom1-pins`Kisdmmcsdmmc-bus4@Khsdmmc-clkKesdmmc-cmdKfsdmmc-detKgspdif0spdif1spi0spi0m0-pins0Kspi0m0-cs0Kspi0m0-cs1Kspi1spi1m1-pins0Kspi1m1-cs0Kspi1m1-cs1Kspi2spi2m2-pins0K spi2m2-cs0K spi2m2-cs1Kspi3spi3m1-pins0K spi3m1-cs0Kspi3m1-cs1Kspi4spi4m0-pins0Kspi4m0-cs0Kspi4m0-cs1Ktsadctsadc-shutKuart0uart0m1-xfer K (uart1uart1m1-xfer K  uart2uart2m0-xfer K uart3uart3m1-xfer K  uart4uart4m1-xfer K  uart5uart5m1-xfer K  uart6uart6m1-xfer K  uart7uart7m1-xfer K  uart8uart8m1-xfer K  uart9uart9m1-xfer K  vopbt656gpio-functsadc-gpio-funcKvideo-codec@fdc70000rockchip,rk3588-av1-vpulvdpu2ACBׄׄ+AC aclkhclk 9chosenYserial2:1500000n8 compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellsphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsrockchip,grfpinctrl-0pinctrl-namesreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthno-sdiono-sdnon-removablemmc-hs400-1_8vmmc-hs400-enhanced-stroberockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsbitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsstdout-path