8( 0coolpi,pi-cm5-evbcoolpi,pi-cm5rockchip,rk3588 +7RK3588 CoolPi CM5 EVBaliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/mmc@fe2e0000/mmc@fe2c0000/mmc@fe2d0000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cluster2core0core1 cpu@0cpuarm,cortex-a55psci"5 < L0,a q~@@  cpu@100cpuarm,cortex-a55psci"5 a q~@@ cpu@200cpuarm,cortex-a55psci"5 a q~@@ cpu@300cpuarm,cortex-a55psci"5 a q~@@ cpu@400cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@500cpuarm,cortex-a76psci"5 a q~@@cpu@600cpuarm,cortex-a76psci"5 < L0,a q~@@cpu@700cpuarm,cortex-a76psci"5 a q~@@ idle-statespscicpu-sleeparm,idle-state#4Kd\xl l2-cache-l0caches@} l2-cache-l1caches@}l2-cache-l2caches@}l2-cache-l3caches@}l2-cache-b0caches@}l2-cache-b1caches@}l2-cache-b2caches@}l2-cache-b3caches@}l3-cachecaches0@}firmwareopteelinaro,optee-tzsmcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0smcclock-0 fixed-clock)׫splldisplay-subsystemrockchip,display-subsystemtimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemusb@fc800000"rockchip,rk3588-ehcigeneric-ehci5 usb*okayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci5 usb*okayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci5  !usb*okayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci5  !usb*okayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(5jihkr&1ref_clksuspend_clkbus_clkutmipipe=host " usb3-phy Eutmi_wideN4Um *disabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXosyscon@fd58c000rockchip,rk3588-sys-grfsysconX(syscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ )syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ*syscon@fd5b0000rockchip,rk3588-php-grfsyscon[$syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@8000rockchip,rk3588-usb2phyNophyapb51phyclk usb480m_phy2*okayhost-port*okay#syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2-phy@c000rockchip,rk3588-usb2phyNp phyapb51phyclk usb480m_phy3*okay host-port*okay#!syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|<]q@LA.2Fq)׫ׄe/ׄ eZ р  $i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=5ts 1i2cpclk%$default+*okayregulator@42rockchip,rk8602B2Ovdd_cpu_big0_s0^rdp&regulator-state-memregulator@43 rockchip,rk8603rockchip,rk8602C2Ovdd_cpu_big1_s0^rdp&regulator-state-memvop@fdd90000rockchip,rk3588-vop BPvopgamma-lut85]\abcd[71aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop' ()* + *disabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~5]\ 1aclkiface- *disabled'serial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK51baudclkapb_pclk:,,?txrx-$defaultIS *disabledpwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5 1pwmpclk.$default` *disabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5 1pwmpclk/$default` *disabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5 1pwmpclk0$default`*okaypwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05 1pwmpclk1$default` *disabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfd+power-controller!rockchip,rk3588-power-controllerk+*okaypower-domain@8k+power-domain@9  5!#" 234k+power-domain@10 5!#"5kpower-domain@11 5!#"6kpower-domain@12 5789:kpower-domain@13 +kpower-domain@14(5;kpower-domain@15 5<kpower-domain@165 =>?+kpower-domain@17 5 @ABkpower-domain@215 CDEFGHIJ+kpower-domain@235CAKkpower-domain@14 5;kpower-domain@155<kpower-domain@225Lkpower-domain@245[Z]MN+kpower-domain@2585ZOkpower-domain@2685QPQkpower-domain@2705RSTU+kpower-domain@28 5VWkpower-domain@29(5XYkpower-domain@305z{Zkpower-domain@31@5W[\]^kpower-domain@33!5WZ[kpower-domain@34"5WZ[kpower-domain@37%52_kpower-domain@38&545kpower-domain@40(`ki2s@fddc0000rockchip,rk3588-i2s-tdm51mclk_txmclk_rxhclk<:a?txNtx-m *disabledi2s@fddf0000rockchip,rk3588-i2s-tdm54451mclk_txmclk_rxhclk<1:a?txNtx-m *disabledi2s@fddfc000rockchip,rk3588-i2s-tdm500,1mclk_txmclk_rxhclk<-:a?rxNrx-m *disabledqos@fdf35000rockchip,rk3588-qossysconP 7qos@fdf35200rockchip,rk3588-qossysconR 8qos@fdf35400rockchip,rk3588-qossysconT 9qos@fdf35600rockchip,rk3588-qossysconV :qos@fdf36000rockchip,rk3588-qossyscon` Zqos@fdf39000rockchip,rk3588-qossyscon _qos@fdf3d800rockchip,rk3588-qossyscon `qos@fdf3e000rockchip,rk3588-qossyscon \qos@fdf3e200rockchip,rk3588-qossyscon [qos@fdf3e400rockchip,rk3588-qossyscon ]qos@fdf3e600rockchip,rk3588-qossyscon ^qos@fdf40000rockchip,rk3588-qossyscon Xqos@fdf40200rockchip,rk3588-qossyscon Yqos@fdf40400rockchip,rk3588-qossyscon Rqos@fdf40500rockchip,rk3588-qossyscon Sqos@fdf40600rockchip,rk3588-qossyscon Tqos@fdf40800rockchip,rk3588-qossyscon Uqos@fdf41000rockchip,rk3588-qossyscon Vqos@fdf41100rockchip,rk3588-qossyscon Wqos@fdf60000rockchip,rk3588-qossyscon =qos@fdf60200rockchip,rk3588-qossyscon >qos@fdf60400rockchip,rk3588-qossyscon ?qos@fdf61000rockchip,rk3588-qossyscon @qos@fdf61200rockchip,rk3588-qossyscon Aqos@fdf61400rockchip,rk3588-qossyscon Bqos@fdf62000rockchip,rk3588-qossyscon ;qos@fdf63000rockchip,rk3588-qossyscon0 <qos@fdf64000rockchip,rk3588-qossyscon@ Kqos@fdf66000rockchip,rk3588-qossyscon` Cqos@fdf66200rockchip,rk3588-qossysconb Dqos@fdf66400rockchip,rk3588-qossyscond Eqos@fdf66600rockchip,rk3588-qossysconf Fqos@fdf66800rockchip,rk3588-qossysconh Gqos@fdf66a00rockchip,rk3588-qossysconj Hqos@fdf66c00rockchip,rk3588-qossysconl Iqos@fdf66e00rockchip,rk3588-qossysconn Jqos@fdf67000rockchip,rk3588-qossysconp Lqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 5qos@fdf71000rockchip,rk3588-qossyscon 6qos@fdf72000rockchip,rk3588-qossyscon 2qos@fdf72200rockchip,rk3588-qossyscon" 3qos@fdf72400rockchip,rk3588-qossyscon$ 4qos@fdf80000rockchip,rk3588-qossyscon Oqos@fdf81000rockchip,rk3588-qossyscon Pqos@fdf81200rockchip,rk3588-qossyscon Qqos@fdf82000rockchip,rk3588-qossyscon Mqos@fdf82200rockchip,rk3588-qossyscon" Npcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?05CH>MR)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`bbbb 0c0 " pcie-phy"T @ @0 @@dbiapbconfigN). pwrpipe+*okay d(e$defaultfghijlegacy-interrupt-controller8 bpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O05DI?NSs)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`kkkk @c@ l pcie-phy"T @ @0 A@dbiapbconfigN*/ pwrpipe+*okay m(e$defaultnlegacy-interrupt-controller8 kdfi@fe060000rockchip,rk3588-dfi@&0: oethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(567Y^501stmmacethclk_mac_refpclk_macaclk_macptp_ref!N$ stmmaceth (M$^pnqr *disabledmdiosnps,dwmac-mdio+stmmac-axi-configprx-queues-configqqueue0queue1tx-queues-configrqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(5b_eTo1satapmaliverxoobrefasic+ *disabledsata-port@0@ l sata-phy# 2 sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(5dagVq1satapmaliverxoobrefasic+ *disabledsata-port@0@ " sata-phy# 2 spi@fe2b0000 rockchip,sfc+@5/01clk_sfchclk_sfc+ *disabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ 5  1biuciuciu-driveciu-sampleALр$defaultstuv(*okayZdvwmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ 51biuciuciu-driveciu-sampleAL $defaultx% *disabledmmc@fe2e0000rockchip,rk3588-dwcmshc.<-., L n6 (5,*+-.1corebusaxiblocktimerL yz{|}$default(Ncorebusaxiblocktimer*okayZi2s@fe470000rockchip,rk3588-i2s-tdmG5+/(1mclk_txmclk_rxhclk<)-:,,?txrx&N*+ tx-mrx-m$default~*okayportendpointi2s'i2s@fe480000rockchip,rk3588-i2s-tdmH5y}u1mclk_txmclk_rxhclk:,,?txrxN^_ tx-mrx-m$default( *disabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI51i2s_clki2s_hclk<:?txrx&$default *disabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ5%1i2s_clki2s_hclk<":?txrx&$default *disabledinterrupt-controller@fe600000 arm,gic-v3 `h 87aA8L+msi-controller@fe640000arm,gic-v3-itsdL[cmsi-controller@fe660000arm,gic-v3-itsfL[ppi-partitionsinterrupt-partition-0finterrupt-partition-1f dma-controller@fea10000arm,pl330arm,primecell@ VWo5n 1apb_pclk,dma-controller@fea30000arm,pl330arm,primecell@ XYo5o 1apb_pclki2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c5{ 1i2cpclk>$default+ *disabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c5| 1i2cpclk?$default+*okayregulator@42rockchip,rk8602B2 Ovdd_npu_s0^rdp~&regulator-state-memi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c5} 1i2cpclk@$default+ *disabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c5~ 1i2cpclkA$default+ *disabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkB$default+ *disabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !5TW 1pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt5dc 1tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF51spiclkapb_pclk:,,?txrx $default+ *disabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG51spiclkapb_pclk:,,?txrx $default+ *disabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH51spiclkapb_pclk:?txrx$default+*okay<L pmic@0rockchip,rk806 $defaultB@&&&&& & & & && 2& ? L& Y f s&dvs1-null-pins gpio_pwrctrl2 pin_fun0dvs2-null-pins gpio_pwrctrl2 pin_fun0dvs3-null-pins gpio_pwrctrl3 pin_fun0regulatorsdcdc-reg1rdp~0 Ovdd_gpu_s0 regulator-state-memdcdc-reg2^rdp~0Ovdd_cpu_lit_s0 regulator-state-memdcdc-reg3^r L q0 Ovdd_log_s0regulator-state-mem qdcdc-reg4^rdp~0 Ovdd_vdenc_s0regulator-state-memdcdc-reg5^r L 0 Ovdd_ddr_s0regulator-state-mem Pdcdc-reg6^r Ovdd2_ddr_s3regulator-state-mem dcdc-reg7^r0Ovdd_2v0_pldo_s3regulator-state-mem  dcdc-reg8^r2Z2Z Ovcc_3v3_s3regulator-state-mem  2Zdcdc-reg9^r Ovddq_ddr_s0regulator-state-memdcdc-reg10^rw@w@ Ovcc_1v8_s3regulator-state-mem  w@pldo-reg1^rw@w@ Oavcc_1v8_s0regulator-state-mempldo-reg2^rw@w@ Ovcc_1v8_s0regulator-state-mem w@pldo-reg3^rOO Oavdd_1v2_s0regulator-state-mempldo-reg4^r2Z2Z0 Ovcc_3v3_s0regulator-state-mempldo-reg5^rw@2Z0 Ovccio_sd_s0wregulator-state-mempldo-reg6^rw@w@ Opldo6_s3regulator-state-mem  w@nldo-reg1^r q q Ovdd_0v75_s3regulator-state-mem  qnldo-reg2^r P POvdd_ddr_pll_s0regulator-state-mem Pnldo-reg3^r q q Oavdd_0v75_s0regulator-state-memnldo-reg4^r P P Ovdd_0v85_s0regulator-state-memnldo-reg5^r q q Ovdd_0v75_s0regulator-state-memspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI51spiclkapb_pclk:?txrx $default+ *disabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL51baudclkapb_pclk:,, ?txrx$defaultSI *disabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM51baudclkapb_pclk:, , ?txrx$defaultSI*okayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN51baudclkapb_pclk:, , ?txrx$defaultSI *disabledserial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO51baudclkapb_pclk: ?txrx$defaultSI *disabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP51baudclkapb_pclk: ?txrx$defaultSI *disabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ51baudclkapb_pclk: ?txrx$defaultSI *disabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR51baudclkapb_pclk:aa?txrx$defaultSI *disabledserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS51baudclkapb_pclk:a a ?txrx$defaultSI *disabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT51baudclkapb_pclk:a a ?txrx$defaultSI *disabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK 1pwmpclk$default` *disabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5LK 1pwmpclk$default` *disabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5LK 1pwmpclk$default` *disabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05LK 1pwmpclk$default` *disabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON 1pwmpclk$default` *disabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5ON 1pwmpclk$default` *disabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5ON 1pwmpclk$default` *disabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05ON 1pwmpclk$default` *disabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ 1pwmpclk$default` *disabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm5RQ 1pwmpclk$default` *disabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm 5RQ 1pwmpclk$default` *disabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm05RQ 1pwmpclk$default` *disabledtsadc@fec00000rockchip,rk3588-tsadc51tsadcapb_pclk<LNVWtsadc-apbtsadc    & $gpiootpout 0*okayadc@fec10000rockchip,rk3588-saradc F51saradcapb_pclkNU saradc-apb*okay Xi2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkC$default+*okayrtc@51haoyu,hym8563Q hym8563$default di2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkD$default+*okayaudio-codec@10everest,es8316<1L511mclkportendpoint'i2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c5 1i2cpclkE$default+ *disabledspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ51spiclkapb_pclk:a a?txrx $default+ *disabledefuse@fecc0000rockchip,rk3588-otp 51otpapb_pclkphyarbN otpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c rnpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[o5p 1apb_pclkaphy@fee00000rockchip,rk3588-naneng-combphy5vW 1refapbpipe<LN<Cphyapb w$ *okaylphy@fee20000rockchip,rk3588-naneng-combphy5xW 1refapbpipe<LN>Ephyapb w$ *okay"sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl +gpio@fd8a0000rockchip,gpio-bank5qr 8gpio@fec20000rockchip,gpio-bank5st 8gpio@fec30000rockchip,gpio-bank5uv @ 8gpio@fec40000rockchip,gpio-bank5wx ` 8mgpio@fec50000rockchip,gpio-bank5yz 8dpcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-2  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-rstnout yemmc-bus8 zemmc-clk {emmc-cmd |emmc-data-strobe }eth1fspigmac1gpuhdmii2c0i2c0m2-xfer %i2c1i2c1m0-xfer  i2c2i2c2m0-xfer   i2c3i2c3m0-xfer   i2c4i2c4m0-xfer   i2c5i2c5m0-xfer   i2c6i2c6m0-xfer   i2c7i2c7m0-xfer   i2c8i2c8m0-xfer   i2s0i2s0-lrck ~i2s0-mclk i2s0-sclk i2s0-sdi0 i2s0-sdo0 i2s1i2s1m0-lrck i2s1m0-sclk i2s1m0-sdi0 i2s1m0-sdi1 i2s1m0-sdi2 i2s1m0-sdi3 i2s1m0-sdo0  i2s1m0-sdo1  i2s1m0-sdo2  i2s1m0-sdo3  i2s2i2s2m1-lrck i2s2m1-sclk  i2s2m1-sdi  i2s2m1-sdo  i2s3i2s3-lrck i2s3-sclk i2s3-sdi i2s3-sdo jtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pdm0pdm1pmicpmic-pinsp pmupwm0pwm0m0-pins .pwm1pwm1m0-pins /pwm2pwm2m0-pins 0pwm3pwm3m0-pins 1pwm4pwm4m0-pins  pwm5pwm5m0-pins pwm6pwm6m0-pins  pwm7pwm7m0-pins  pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins  pwm12pwm12m0-pins  pwm13pwm13m0-pins  pwm14pwm14m0-pins  pwm15pwm15m0-pins  refclksatasata0sata1sata2sdiosdiom1-pins` xsdmmcsdmmc-bus4@ vsdmmc-clk ssdmmc-cmd tsdmmc-det uspdif0spdif1spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m1-pins0 spi1m1-cs0 spi1m1-cs1 spi2spi2m2-pins0  spi2m2-cs0 spi3spi3m1-pins0  spi3m1-cs0 spi3m1-cs1 spi4spi4m0-pins0 spi4m0-cs0 spi4m0-cs1 tsadctsadc-shut uart0uart0m1-xfer  -uart1uart1m1-xfer   uart2uart2m0-xfer  uart3uart3m1-xfer   uart4uart4m1-xfer   uart5uart5m1-xfer   uart6uart6m1-xfer   uart7uart7m1-xfer   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d(elegacy-interrupt-controller8 pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+05AF<KPu)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr`   pcie-phy"T @ @@0 @@@dbiapbconfigN', pwrpipe*okay m(elegacy-interrupt-controller8 pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /05BG=LQ)1aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr` c   pcie-phy"T @ @0 @@dbiapbconfigN(- pwrpipe+ *disabledlegacy-interrupt-controller8 ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(567X]401stmmacethclk_mac_refpclk_macaclk_macptp_ref!N# stmmaceth (M$^n*okay output  rgmii-rxid$default ' 0Cmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22$default 9N  I d stmmac-axi-configrx-queues-configqueue0queue1tx-queues-configqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(5c`fUp1satapmaliverxoobrefasic+*okaysata-port@0@  sata-phy# 2 phy@fee10000rockchip,rk3588-naneng-combphy5wW 1refapbpipe<LN=Dphyapb w$ *okayphy@fee80000rockchip,rk3588-pcie3-phy5y1pclkNHphy w$ [*okayanalog-soundaudio-graph-card l qrk3588-es8316. wMIC2Mic JackHeadphonesHPOLHeadphonesHPOR) MicrophoneMic JackHeadphoneHeadphoneschosen serial2:1500000n8avdd0v85-pcie20-regulatorregulator-fixedOavdd0v85_pcie20r^ P Pavdd1v8-pcie20-regulatorregulator-fixedOavdd1v8_pcie20r^w@w@avdd0v75-pcie30-regulatorregulator-fixedOavdd0v75_pcie30r^ q qavdd1v8-pcie30-regulatorregulator-fixedOpcie30_avdd1v8r^w@w@backlightpwm-backlight d$default  aleds gpio-ledsled-0  status "m heartbeatvcc12v-dcin-regulatorregulator-fixed Ovcc12v_dcin^rvcc5v0-sys-regulatorregulator-fixed Ovcc5v0_sys^rLK@LK@&vcc3v3-sys-regulatorregulator-fixed Ovcc3v3_sys^r2Z2Zevcc3v3-lcd-regulatorregulator-fixed Ovcc3v3_lcd  $defaultevcc5v0-usb-host-regulatorregulator-fixed Ovcc5v0_hostr^ LK@LK@ $default&#vcc5v0-usb30-otg-regulatorregulator-fixed Ovcc5v0_otgr^ LK@LK@ "$default& compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesportsinterrupt-namesrangesphysphy-namespower-domainsstatusclock-namesdr_modephy_typeresetssnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirkreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmu#iommu-cellsdmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplyinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpno-sdiono-mmcsd-uhs-sdr104vqmmc-supplymmc-hs400-1_8vmmc-hs400-enhanced-strobeno-sdnon-removablerockchip,trcm-sync-tx-onlydai-formatmclk-fsremote-endpointmbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csgpio-controller#gpio-cellsspi-max-frequencyvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplywakeup-sourcebitsrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsclock_in_outphy-handlephy-moderx_delaytx_delayreset-assert-usreset-deassert-usrockchip,phy-grfdaislabelroutingwidgetsstdout-pathenable-gpiospower-supplypwmscolorlinux,default-triggerenable-active-highgpio