8D( 'friendlyarm,nanopi-r2crockchip,rk3328 +7FriendlyElec NanoPi R2Caliases=/pinctrl/gpio@ff210000C/pinctrl/gpio@ff220000I/pinctrl/gpio@ff230000O/pinctrl/gpio@ff240000U/serial@ff110000]/serial@ff120000e/serial@ff130000m/i2c@ff150000r/i2c@ff160000w/i2c@ff170000|/i2c@ff180000/ethernet@ff540000/usb@ff600000/device@2/mmc@ff500000cpus+cpu@0cpuarm,cortex-a53xpsci ( cpu@1cpuarm,cortex-a53xpsci ( cpu@2cpuarm,cortex-a53xpsci ( cpu@3cpuarm,cortex-a53xpsci ( idle-states0pscicpu-sleeparm,idle-state=Nexv(l2-cache0cache(opp-table-0operating-points-v2(opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2s!Analog 8disabledsimple-audio-card,cpu?simple-audio-card,codec?arm-pmuarm,cortex-a53-pmu0IdefgT display-subsystemrockchip,display-subsystemg  8disabledhdmi-soundsimple-audio-cardi2s!HDMI 8disabledsimple-audio-card,cpu?simple-audio-card,codec?psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0I   xin24m fixed-clockmzn6xin24m(Ei2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s I)7i2s_clki2s_hclk  txrx 8disabled(i2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s I*8i2s_clki2s_hclktxrx 8disabled(i2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s I+9i2s_clki2s_hclktxrx 8disabledspdif@ff030000rockchip,rk3328-spdif I.: mclkhclk txdefault 8disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep 8disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd(:io-domains"rockchip,rk3328-io-voltage-domain8okay"0>gpiorockchip,rk3328-grf-gpioL\power-controller!rockchip,rk3328-power-controllerh+(<power-domain@6hpower-domain@5 BABhpower-domain@8Fhreboot-modesyscon-reboot-mode|RBRBRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart I7&baudclkapb_pclktxrxdefault  !" 8disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart I8'baudclkapb_pclktxrxdefault #$% 8disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart I9(baudclkapb_pclktxrxdefault&8okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c I$+7 i2cpclkdefault' 8disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c I%+8 i2cpclkdefault(8okaypmic@18rockchip,rk805 )Imxin32krk805-clkout2L\*default+ ++#+/;+regulatorsDCDC_REG1Gvdd_logVj| 4 0regulator-state-memB@DCDC_REG2Gvdd_armVj| 4 0(regulator-state-mem~DCDC_REG3Gvcc_ddrVjregulator-state-memDCDC_REG4 Gvcc_io_33Vj|2Z2Z(regulator-state-mem2ZLDO_REG1Gvcc_18Vj|w@w@(regulator-state-memw@LDO_REG2 Gvcc18_emmcVj|w@w@(regulator-state-memw@LDO_REG3Gvdd_10Vj|B@B@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c I&+9 i2cpclkdefault, 8disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c I'+: i2cpclkdefault- 8disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi I1+ spiclkapb_pclk txrxdefault./01 8disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt I(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault2 8disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault3 8disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault48okaypwm@ff1b0030rockchip,rk3328-pwm0< pwmpclkdefault5 8disableddma-controller@ff1f0000arm,pl330arm,primecell@I apb_pclk(thermal-zonessoc-thermal"8FX6tripstrip-point0hptpassivetrip-point1hLtpassive(7soc-crithst criticalcooling-mapsmap070 tsadc@ff250000rockchip,rk3328-tsadc% I:$P$tsadcapb_pclkinitdefaultsleep898B tsadc-apb:8okay3(6efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuseN id@7cpu-leakage@17logic-leakage@19cpu-version@1ab(Fadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( IPg%saradcapb_pclkV saradc-apb 8disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TIZW]XY[\"ygpgpmmupppp0ppmmu0pp1ppmmu1 buscorefiommu@ff330200rockchip,iommu3 I` aclkiface 8disablediommu@ff340800rockchip,iommu4@ IbF aclkiface 8disabledvideo-codec@ff350000rockchip,rk3328-vpu5 I yvdpuF aclkhclk;<iommu@ff350800rockchip,iommu5@ I F aclkiface<(;video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 I BABaxiahbcabaccoreAB ׄׄ=<iommu@ff360480rockchip,iommu 6@6@ IJB aclkiface<(=vop@ff370000rockchip,rk3328-vop7> I x;aclk_vopdclk_vophclk_vop axiahbdclk> 8disabledport+( endpoint@0?(Diommu@ff373f00rockchip,iommu7? I ; aclkiface 8disabled(>hdmi@ff3c0000rockchip,rk3328-dw-hdmi<I#GFiahbisfrcec@hdmidefault ABC: 8disabled(ports+port@0endpointD(?port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk: 8disabled(phy@ff430000rockchip,rk3328-hdmi-phyC ISEysysclkrefoclkrefpclk hdmi_phymF cpu-version 8disabled(@clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD:mx=&'(ABDC"\5H4$zEEE|n6n6n6n6#FLGрxhxhрxhxh(syscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEphyclk usb480m_phym{G8okay(Gotg-port$I;<=yotg-bvalidotg-idlinestate8okay(Thost-port I> ylinestate8okay(Ummc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ I  =!JNbiuciuciu-driveciu-sample!р8okay/9JHIJKdefaultUbo|Lmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ I  >"KObiuciuciu-driveciu-sample!р 8disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ I ?#LPbiuciuciu-driveciu-sample!р 8disabledethernet@ff540000rockchip,rk3328-gmacT Iymacirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth:8okaydfMMinputNrgmiiOdefault"mdiosnps,dwmac-mdio+ethernet-phy@3ethernet-phy-ieee802.3-c22sY@0KPdefaulti'yP )(Nethernet@ff550000rockchip,rk3328-gmacU: Iymacirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiQoutput 8disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultRS(Qusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X IMotghost@ T usb2-phy8okayusb@ff5c0000 generic-ehci\ I NGUusb8okayusb@ff5d0000 generic-ohci] I NGUusb8okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` IC`aref_clksuspend_clkbus_clkhost utmi_wide  # E f 8okay+device@2 usbbda,8153interrupt-controller@ff811000 arm,gic-400  @ @ `  I (crypto@ff060000rockchip,rk3328-crypto@ IPQ;hclk_masterhclk_slavesclkD crypto-rstpinctrlrockchip,rk3328-pinctrl:+ gpio@ff210000rockchip,gpio-bank! I3L\  (bgpio@ff220000rockchip,gpio-bank" I4L\  ()gpio@ff230000rockchip,gpio-bank# I5L\  (fgpio@ff240000rockchip,gpio-bank$ I6L\  pcfg-pull-up (Xpcfg-pull-down (`pcfg-pull-none (Vpcfg-pull-none-2ma  (_pcfg-pull-up-2ma  pcfg-pull-up-4ma  (Ypcfg-pull-none-4ma  (\pcfg-pull-down-4ma  pcfg-pull-none-8ma  (Zpcfg-pull-up-8ma  ([pcfg-pull-none-12ma  (]pcfg-pull-up-12ma  (^pcfg-output-high pcfg-output-low pcfg-input-high  (Wpcfg-input i2c0i2c0-xfer !VV('i2c1i2c1-xfer !VV((i2c2i2c2-xfer ! VV(,i2c3i2c3-xfer !VV(-i2c3-pins !VVhdmi_i2chdmii2c-xfer !VV(Bpdm-0pdmm0-clk !V(pdmm0-fsync !Vpdmm0-sdi0 !V(pdmm0-sdi1 !V(pdmm0-sdi2 !V(pdmm0-sdi3 !V(pdmm0-clk-sleep !W(pdmm0-sdi0-sleep !W(pdmm0-sdi1-sleep !W(pdmm0-sdi2-sleep !W(pdmm0-sdi3-sleep !W(pdmm0-fsync-sleep !Wtsadcotp-pin ! V(8otp-out ! V(9uart0uart0-xfer ! VX( uart0-cts ! V(!uart0-rts ! V("uart0-rts-pin ! Vuart1uart1-xfer !VX(#uart1-cts !V($uart1-rts !V(%uart1-rts-pin !Vuart2-0uart2m0-xfer !VXuart2-1uart2m1-xfer !VX(&spi0-0spi0m0-clk !Xspi0m0-cs0 ! Xspi0m0-tx ! Xspi0m0-rx ! Xspi0m0-cs1 ! Xspi0-1spi0m1-clk !Xspi0m1-cs0 !Xspi0m1-tx !Xspi0m1-rx !Xspi0m1-cs1 !Xspi0-2spi0m2-clk !X(.spi0m2-cs0 !X(1spi0m2-tx !X(/spi0m2-rx !X(0i2s1i2s1-mclk !Vi2s1-sclk !Vi2s1-lrckrx !Vi2s1-lrcktx !Vi2s1-sdi !Vi2s1-sdo !Vi2s1-sdio1 !Vi2s1-sdio2 !Vi2s1-sdio3 !Vi2s1-sleep !WWWWWWWWWi2s2-0i2s2m0-mclk !Vi2s2m0-sclk !Vi2s2m0-lrckrx !Vi2s2m0-lrcktx !Vi2s2m0-sdi !Vi2s2m0-sdo !Vi2s2m0-sleep` !WWWWWWi2s2-1i2s2m1-mclk !Vi2s2m1-sclk !Vi2sm1-lrckrx !Vi2s2m1-lrcktx !Vi2s2m1-sdi !Vi2s2m1-sdo !Vi2s2m1-sleepP !WWWWWspdif-0spdifm0-tx !Vspdif-1spdifm1-tx !Vspdif-2spdifm2-tx !V(sdmmc0-0sdmmc0m0-pwren !Ysdmmc0m0-pin !Ysdmmc0-1sdmmc0m1-pwren !Ysdmmc0m1-pin !Y(hsdmmc0sdmmc0-clk !Z(Hsdmmc0-cmd ![(Isdmmc0-dectn !Y(Jsdmmc0-wrprt !Ysdmmc0-bus1 ![sdmmc0-bus4@ ![[[[(Ksdmmc0-pins !YYYYYYYYsdmmc0extsdmmc0ext-clk !\sdmmc0ext-cmd !Ysdmmc0ext-wrprt !Ysdmmc0ext-dectn !Ysdmmc0ext-bus1 !Ysdmmc0ext-bus4@ !YYYYsdmmc0ext-pins !YYYYYYYYsdmmc1sdmmc1-clk ! Zsdmmc1-cmd ! [sdmmc1-pwren ![sdmmc1-wrprt ![sdmmc1-dectn ![sdmmc1-bus1 ![sdmmc1-bus4@ ![[[[sdmmc1-pins ! Y YYYYYYYYemmcemmc-clk !]emmc-cmd !^emmc-pwren !Vemmc-rstnout !Vemmc-bus1 !^emmc-bus4@ !^^^^emmc-bus8 !^^^^^^^^pwm0pwm0-pin !V(2pwm1pwm1-pin !V(3pwm2pwm2-pin !V(4pwmirpwmir-pin !V(5gmac-1rgmiim1-pins` ! Z \\Z\\\ \ \Z Z\\ZZZ Z\ZZZZ(Ormiim1-pins !_]____ _ _] ] V VVVVVgmac2phyfephyled-speed10 !Vfephyled-duplex !Vfephyled-rxm1 !V(Rfephyled-txm1 !Vfephyled-linkm1 !V(Stsadc_pintsadc-int ! Vtsadc-pin ! Vhdmi_pinhdmi-cec !V(Ahdmi-hpd !`(Ccif-0dvp-d2d9-m0 !VVVVV V V VVVVVcif-1dvp-d2d9-m1 !VVVVVVVVVVVVbuttonreset-button-pin !V(agmac2ioeth-phy-reset-pin !`(Pledslan-led-pin !V(csys-led-pin !V(dwan-led-pin !V(elanlan-vdd-pin !V(ipmicpmic-int-l !X(*sdsdio-vcc-pin !X(gchosen /serial2:1500000n8gmac-clock fixed-clockzsY@ gmac_clkinm(Mkeys gpio-keysadefaultkey-reset ;reset b A L2leds gpio-leds cdedefaultled-0 f ;nanopi-r2s:green:lanled-1 b ;nanopi-r2s:red:sys ^onled-2 f ;nanopi-r2s:green:wansdmmcio-regulatorregulator-gpio l )gdefault Gvcc_io_sdioV|w@2Z  voltage w@2Z (sdmmc-regulatorregulator-fixed bhdefaultGvcc_sdj|2Z2Z (Lvdd-5vregulator-fixedGvdd_5vVj|LK@LK@(+vdd-5v-lanregulator-fixed l fidefault Gvdd_5v_lanVj + compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3serial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplytx-fifo-depthrx-fifo-depthsnps,txpblclock_in_outphy-handlephy-modephy-supplyrx_delaysnps,aaltx_delaymotorcomm,clk-out-frequency-hzmotorcomm,keep-pll-enabledmotorcomm,auto-sleep-disabledreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathlabellinux,codedebounce-intervaldefault-stateenable-active-highregulator-settling-time-usregulator-typestartup-delay-usvin-supplygpio