8{({Tradxa,rockpisrockchip,rk3308 +7Radxa ROCK Pi Saliases=/pinctrl/gpio@ff220000C/pinctrl/gpio@ff230000I/pinctrl/gpio@ff240000O/pinctrl/gpio@ff250000U/pinctrl/gpio@ff260000[/i2c@ff040000`/i2c@ff050000e/i2c@ff060000j/i2c@ff070000o/serial@ff0a0000w/serial@ff0b0000/serial@ff0c0000/serial@ff0d0000/serial@ff0e0000/spi@ff120000/spi@ff130000/spi@ff140000/ethernet@ff4e0000/mmc@ff490000/mmc@ff480000cpus+cpu@0cpuarm,cortex-a35psciZ,=Hcpu@1cpuarm,cortex-a35psci,Hcpu@2cpuarm,cortex-a35psci,H cpu@3cpuarm,cortex-a35psci,H idle-statesPpscicpu-sleeparm,idle-state]nxHl2-cachecacheHopp-table-0operating-points-v2Hopp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock, syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+okayi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt  okayserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk)default okayserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk)default  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk)default disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclk)default disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclk)default okaybluetoothrealtek,rtl8723bs-bt 6  H spi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclkX]txrxdefault ! disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclkX]txrxdefault"#$% disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclkX&&]txrxdefault'()* disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault+g disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault,g disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault-g disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault.g disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault/g disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault0g disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault1g disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault2g disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault3gokayHgpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault4g disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault5g disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault6g disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclkrF saradc-apbokay7dma-controller@ff2c0000arm,pl330arm,primecell,@ apb_pclkHdma-controller@ff2d0000arm,pl330arm,primecell-@ apb_pclkH&i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclkX&& ]txrxreset-mreset-hdefault89:; disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclkX& ]rxreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclkX& ]txdefault< disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ Botg peripheral@ = usb2-phyokayusb@ff440000 generic-ehciD G >usbokayusb@ff450000 generic-ohciE H >usbokaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L  012biuciuciu-driveciu-sample!рdefault?@ABokay/mmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M  :;<biuciuciu-driveciu-sample!рokay@RaoCmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N  567biuciuciu-driveciu-sample!B@default DEFokay+/{Ganand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfc-рHIJKLMNdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedrmiidefaultOP} stmmacethQokayoutputC R PPspi@ff4c0000 rockchip,sfcL@ R=clk_sfchclk_sfc STUdefault disabledclock-controller@ff500000rockchip,rk3308-cruPVxin24mQO*Hinterrupt-controller@ff580000 arm,gic-400@XX X@ X`   7HHsram@fff80000 mmio-sram]+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlQ+]defaultWgpio@ff220000rockchip,gpio-bank" (dtH7header1-pin3 [GPIO0_B3]header1-pin5 [GPIO0_B4]header1-pin11 [GPIO0_B7]header1-pin13 [GPIO0_C0]header1-pin15 [GPIO0_C1]HRgpio@ff230000rockchip,gpio-bank# )dtH7header1-pin21 [GPIO1_C6]header1-pin19 [GPIO1_C7]header1-pin23 [GPIO1_D0]header1-pin24 [GPIO1_D1]gpio@ff240000rockchip,gpio-bank$ *dtH7header1-pin10 [GPIO2_A0]header1-pin8 [GPIO2_A1]header1-pin7 [GPIO2_A4]header1-pin12 [GPIO2_A5]header2-pin46 [GPIO2_A6]header1-pin22 [GPIO1_A7]header2-pin45 [GPIO2_B0]header1-pin18 [GPIO2_B1]header1-pin16 [GPIO2_B2]header2-pin44 [GPIO2_B3]header2-pin43 [GPIO2_B4]header2-pin28 [GPIO2_B5]header2-pin30 [GPIO2_B6]header2-pin32 [GPIO2_B7]header2-pin34 [GPIO2_C0]gpio@ff250000rockchip,gpio-bank% +dtH7header2-pin42 [GPIO3_B2]header2-pin41 [GPIO3_B3]header2-pin40 [GPIO3_B4]header2-pin39 [GPIO3_B5]gpio@ff260000rockchip,gpio-bank& ,dtH7Hpcfg-pull-upHapcfg-pull-downH^pcfg-pull-noneHZpcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4maH`pcfg-pull-none-4maH_pcfg-pull-down-4mapcfg-pull-none-8maHXpcfg-pull-up-8maHYpcfg-pull-none-12ma H\pcfg-pull-up-12ma H[pcfg-pull-none-smtH]pcfg-output-highpcfg-output-lowpcfg-input-highpcfg-inputemmcemmc-clk Xemmc-cmdYemmc-pwren Zemmc-rstn Zemmc-bus1Yemmc-bus4@YYYYemmc-bus8YYYYYYYYflashflash-csn0 ZHKflash-rdy ZHMflash-ale ZHHflash-cle ZHJflash-wrnZHNflash-rdn ZHLflash-bus8[[[[[[[[HIsfcsfc-bus4@ZZZZHUsfc-bus2 ZZsfc-cs0ZHTsfc-clkZHSgmacrmii-pins\\\ZZZZZ ZHOmac-refclk-12ma \HPmac-refclk Zgmac-m1rmiim1-pins\\\ZZZZZ Zmacm1-refclk-12ma \macm1-refclk Zi2c0i2c0-xfer ]]H i2c1i2c1-xfer  ] ]Hi2c2i2c2-xfer ]]Hi2c3-m0i2c3m0-xfer ]]Hi2c3-m1i2c3m1-xfer  ] ]i2c3-m2i2c3m2-xfer ]]i2s_2ch_0i2s-2ch-0-mclk Zi2s-2ch-0-sclk ZH8i2s-2ch-0-lrckZH9i2s-2ch-0-sdoZH;i2s-2ch-0-sdiZH:i2s_8ch_0i2s-8ch-0-mclkZi2s-8ch-0-sclktxZi2s-8ch-0-sclkrxZi2s-8ch-0-lrcktxZi2s-8ch-0-lrckrxZi2s-8ch-0-sdo0 Zi2s-8ch-0-sdo1 Zi2s-8ch-0-sdo2 Zi2s-8ch-0-sdo3 Zi2s-8ch-0-sdi0 Zi2s-8ch-0-sdi1Zi2s-8ch-0-sdi2Zi2s-8ch-0-sdi3Zi2s_8ch_1_m0i2s-8ch-1-m0-mclkZi2s-8ch-1-m0-sclktxZi2s-8ch-1-m0-sclkrxZi2s-8ch-1-m0-lrcktxZi2s-8ch-1-m0-lrckrxZi2s-8ch-1-m0-sdo0Zi2s-8ch-1-m0-sdo1-sdi3Zi2s-8ch-1-m0-sdo2-sdi2 Zi2s-8ch-1-m0-sdo3_sdi1 Zi2s-8ch-1-m0-sdi0 Zi2s_8ch_1_m1i2s-8ch-1-m1-mclk Zi2s-8ch-1-m1-sclktx Zi2s-8ch-1-m1-sclkrxZi2s-8ch-1-m1-lrcktxZi2s-8ch-1-m1-lrckrxZi2s-8ch-1-m1-sdo0Zi2s-8ch-1-m1-sdo1-sdi3Zi2s-8ch-1-m1-sdo2-sdi2Zi2s-8ch-1-m1-sdo3_sdi1Zi2s-8ch-1-m1-sdi0Zpdm_m0pdm-m0-clkZpdm-m0-sdi0 Zpdm-m0-sdi1 Zpdm-m0-sdi2 Zpdm-m0-sdi3Zpdm_m1pdm-m1-clkZpdm-m1-sdi0Zpdm-m1-sdi1Zpdm-m1-sdi2Zpdm-m1-sdi3Zpdm_m2pdm-m2-clkmZpdm-m2-clkZpdm-m2-sdi0 Zpdm-m2-sdi1Zpdm-m2-sdi2Zpdm-m2-sdi3Zpwm0pwm0-pin Zpwm0-pin-pull-down ^H3pwm1pwm1-pinZH4pwm1-pin-pull-down^pwm2pwm2-pinZH5pwm2-pin-pull-down^pwm3pwm3-pinZH6pwm3-pin-pull-down^pwm4pwm4-pinZH/pwm4-pin-pull-down^pwm5pwm5-pinZH0pwm5-pin-pull-down^pwm6pwm6-pinZH1pwm6-pin-pull-down^pwm7pwm7-pinZH2pwm7-pin-pull-down^pwm8pwm8-pin ZH+pwm8-pin-pull-down ^pwm9pwm9-pin ZH,pwm9-pin-pull-down ^pwm10pwm10-pin ZH-pwm10-pin-pull-down ^pwm11pwm11-pinZH.pwm11-pin-pull-down^rtcrtc-32kZHWsdmmcsdmmc-clk_H?sdmmc-cmd`H@sdmmc-det`HAsdmmc-pwren_sdmmc-bus1`sdmmc-bus4@````HBsdiosdio-clkXHFsdio-cmdYHEsdio-pwrenXsdio-wrptXsdio-intnXsdio-bus1Ysdio-bus4@YYYYHDspdif_inspdif-inZspdif_outspdif-outZH<spi0spi0-clk`Hspi0-csn0`Hspi0-miso`H spi0-mosi`H!spi1spi1-clk `H"spi1-csn0 `H#spi1-miso `H$spi1-mosi `H%spi1-m1spi1m1-miso`spi1m1-mosi`spi1m1-clk`spi1m1-csn0 `spi2spi2-clk`H'spi2-csn0`H(spi2-miso`H)spi2-mosi`H*tsadctsadc-otp-pin Ztsadc-otp-out Zuart0uart0-xfer aaHuart0-ctsZHuart0-rtsZHuart0-rts-pinZuart1uart1-xfer aaHuart1-ctsZHuart1-rtsZHuart2-m0uart2m0-xfer aaHuart2-m1uart2m1-xfer aauart3uart3-xfer  a aHuart3-m1uart3m1-xfer aauart4uart4-xfer  aaHuart4-ctsZHuart4-rtsZHuart4-rts-pinZledsgreen-led-gpioZHbheartbeat-led-gpioZHcusbotg-vbus-drvZHfsdio-pwrseqwifi-enable-hZHdwifi-host-wake^chosenserial0:1500000n8leds gpio-ledsdefaultbcgreen-ledon BR)rockpis:green:power /default-onblue-ledon BR)rockpis:blue:user /heartbeatsdio-pwrseqmmc-pwrseq-simpleddefault ERHGvcc-1v8regulator-fixedQvcc_1v8`tw@w@CH7vcc-ioregulator-fixedQvcc_io`t2Z2ZeHCvcc-ddrregulator-fixedQvcc_ddr`t``evcc5v0-otgregulator-fixed Rdefaultf Qvcc5v0_otg`eH vcc5v0-sysregulator-fixed Qvcc5v0_sys`tLK@LK@Hevdd-corepwm-regulatorge Qvdd_core xr``tHvdd-logregulator-fixedQvdd_log`te compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellsphy-supplypinctrl-namespinctrl-0reg-shiftreg-io-widthdevice-wake-gpioshost-wake-gpiosdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-sd-highspeedcap-mmc-highspeedmmc-hs200-1_8vnon-removablevmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr104assigned-clock-ratesphy-moderockchip,grfclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-us#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsgpio-line-namesbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathdefault-statelabellinux,default-triggerreset-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highpwmspwm-supplyregulator-settling-time-up-us