Ð þí068-„(²-LArmadeus Systems APF51 module!armadeus,imx51-apf51fsl,imx51chosenaliases%,/soc/aips@80000000/ethernet@83fec000!6/soc/aips@70000000/gpio@73f84000!ü" mdisabledssi@83fcc000–!fsl,imx51-ssifsl,imx21-ssi¹ƒüÀ@Cü0“ ipgbaud §¬rxtx¶ mdisabledaudmux@83fd0000"!fsl,imx51-audmuxfsl,imx31-audmux¹ƒý@üaudmux mdisabledm4if@83fd8000!fsl,imx51-m4if¹ƒý€weim@83fda000!fsl,imx51-weim¹ƒý ü9`_°¸ÀÈÌÎ mdisablednand@83fdb000!fsl,imx51-nand¹ƒý°ÏÿCü<mokayRahwopata@83fe0000!fsl,imx51-patafsl,imx27-pata¹ƒþ@CFü¬ mdisabledssi@83fe8000–!fsl,imx51-ssifsl,imx21-ssi¹ƒþ€@C`ü2• ipgbaud §./¬rxtx¶ mdisabledethernet@83fec000!fsl,imx51-fecfsl,imx27-fec¹ƒþÀ@CWü*** ipgahbptpmokay~defaultŒ mii Š švpu@83ff4000!fsl,imx51-vpucnm,codahx4¹ƒÿ@C ü@?perahbf­ crypto@83ff8000"!fsl,imx53-saharafsl,imx51-sahara¹ƒÿ€@Cü»»ipgahbmemory@90000000âmemory¹  #address-cells#size-cellsmodelcompatibleethernet0gpio0gpio1gpio2gpio3i2c0i2c1mmc0mmc1mmc2mmc3serial0serial1serial2spi0spi1spi2interrupt-controller#interrupt-cellsregphandle#clock-cellsclock-frequencydevice_typeclock-latencyclocksclock-namesoperating-pointsvoltage-toleranceinterrupt-parentinterrupts#phy-cellsportsrangesresetsstatusbus-widthpinctrl-namespinctrl-0#sound-dai-cellsdmasdma-namesfsl,fifo-depthfsl,usbmiscfsl,usbphydr_mode#index-cellsgpio-controller#gpio-cellsfsl,pins#pwm-cells#reset-cells#dma-cellsfsl,sdma-ram-script-namenand-bus-widthnand-ecc-modenand-on-flash-bbtphy-modephy-reset-gpiosphy-reset-durationiram