Co8>(> ,Huawei Nexus 6P2huawei,anglerqcom,msm8994=I  VZchosendserial0:115200n8clocksxo-board 2fixed-clockp}$ xo_boardsleep-clk 2fixed-clockp} sleep_clkcpus cpu@0cpu2arm,cortex-a53pscil2-cache2cachecpu@1cpu2arm,cortex-a53pscicpu@2cpu2arm,cortex-a53pscicpu@3cpu2arm,cortex-a53pscicpu@100cpu2arm,cortex-a57pscil2-cache2cachecpu@101cpu2arm,cortex-a57psci cpu@102cpu2arm,cortex-a57psci cpu@103cpu2arm,cortex-a57psci cpu-mapcluster0core0core1core2core3cluster1core0core1 core2 core3 firmwarescm2qcom,scm-msm8994qcom,scmmemory@80000000memoryhwlock2qcom,tcsr-mutex pmu2arm,cortex-a53-pmu psci 2arm,psci-0.2hvcreserved-memory dfps_data_mem@3400000@smem_region@6a00000 memory@7000000memory@ca00000 memory@c64000002qcom,rmtfs-mem@memory@c6700000pmemory@c7000000memory@c9400000@smd 2qcom,smdrpm  $ -;Jrpm-requests2qcom,rpm-msm8994 Zrpm_requestsrpmcc2qcom,rpmcc-msm8994ppower-controller2qcom,msm8994-rpmpdlopp-table2operating-points-v2opp1opp2opp3opp4opp5opp6smem 2qcom,smemsmp2p-lpass 2qcom,smp2p  $  ;Jmaster-kernelmaster-kernelslave-kernel slave-kernel smp2p-modem 2qcom,smp2p  $ ;Jmaster-kernelmaster-kernelslave-kernel slave-kernel soc  2simple-businterrupt-controller@f90000002qcom,msm-qgic2  mailbox@f900d000%2qcom,msm8994-apcs-kpss-globalsyscon  timer@f9020000 2arm,armv7-timer-memframe@f9021000(  frame@f9023000( 0 5disabledframe@f9024000( @ 5disabledframe@f9025000( P 5disabledframe@f9026000( ` 5disabledframe@f9027000( p 5disabledframe@f9028000(  5disabledusb@f92f88002qcom,msm8996-dwc3qcom,dwc3/  <rms"Ccoreifacesleepmock_utmirefxoOsr_$'tusb@f9200000 2snps,dwc3   high-speed peripheralsdhci@f98249002qcom,sdhci-msm-v4I@hc_memcore_mem{hc_irqpwr_irq<hvCcoreifacexodefaultsleep", 5disabledsdhci@f98a49002qcom,sdhci-msm-v4I@hc_memcore_mem}hc_irqpwr_irq<iCcoreifacexodefaultsleep   ! :"d" 5disableddma-controller@f99040002qcom,bam-v1.7.0@ <:Cbam_clkCNVo|%serial@f991e000%2qcom,msm-uartdm-v1.4qcom,msm-uartdm l Ccoreiface<H:defaultsleep#$5okayi2c@f99230002qcom,i2c-qup-v2.2.10 _<:; Cifacecore}% % txrxdefaultsleep&'  5disabledspi@f99230002qcom,spi-qup-v2.2.10 _<<: Ccoreiface$% % txrxdefaultsleep()  5disabledi2c@f99240002qcom,i2c-qup-v2.2.1@ `<:= Cifacecore}%%txrxdefaultsleep*+  5disabledi2c@f99260002qcom,i2c-qup-v2.2.1` b<:A Cifacecore}%%txrxdefaultsleep,-  5disabledi2c@f99270002qcom,i2c-qup-v2.2.1p c<:C Cifacecore}..txrxdefaultsleep/0  5disabledi2c@f99280002qcom,i2c-qup-v2.2.1 d<:E Cifacecore}%%txrxdefaultsleep12  5disableddma-controller@f99440002qcom,bam-v1.7.0@ <MCbam_clkCNVo|.serial@f995e000%2qcom,msm-uartdm-v1.4qcom,msm-uartdm r Ccoreiface<[M..txrxdefaultsleep34 5disabledi2c@f99630002qcom,i2c-qup-v2.2.10 e<MN Cifacecore}. . txrxdefaultsleep56  5disabledspi@f99660002qcom,spi-qup-v2.2.1` h<UM Ccoreiface$..txrxdefaultsleep78  5disabledi2c@f99670002qcom,i2c-qup-v2.2.1p i<MV Cifacecore}j..txrxdefaultsleep9:  5disabledclock-controller@fc4000002qcom,gcc-msm8994pl@ sram@fc4280002qcom,rpm-msg-ramB@restart@fc4ab000 2qcom,psholdJspmi@fc4c00002qcom,spmi-pmic-arbLLLcoreintrcnfg periph_irq N  syscon@fd4840002sysconH@  pinctrl@fd5100002qcom,msm8994-pinctrlQ@ " U"blsp1-uart2-default blsp_uart2  gpio4gpio5#blsp1-uart2-sleepgpio  gpio4gpio5+$blsp2-uart2-default blsp_uart8 gpio45gpio46gpio47gpio483blsp2-uart2-sleepgpio gpio45gpio46gpio47gpio484i2c1-default blsp_i2c1  gpio2gpio3&i2c1-sleepgpio  gpio2gpio3'i2c2-default blsp_i2c2  gpio6gpio7*i2c2-sleepgpio  gpio6gpio7+i2c4-default blsp_i2c4 gpio19gpio20,i2c4-sleepgpio gpio19gpio20+:-i2c5-default blsp_i2c5 gpio23gpio24/i2c5-sleepgpio gpio23gpio240i2c6-default blsp_i2c6 gpio28gpio271i2c6-sleepgpio gpio28gpio272i2c7-default blsp_i2c7 gpio44gpio435i2c7-sleepgpio gpio44gpio436blsp2-spi10-default7default blsp_spi10 gpio53gpio54gpio55 +csgpio gpio55blsp2-spi10-sleep gpio53gpio54gpio558i2c11-default blsp_i2c11 gpio83gpio849i2c11-sleepgpio gpio83gpio84:blsp1-spi1-default(default blsp_spi1 gpio0gpio1gpio3 +csgpio gpio8blsp1-spi1-sleep gpio0gpio1gpio3)clk-on  sdc1_clkclk-off  sdc1_clkcmd-on  sdc1_cmdGcmd-off  sdc1_cmdGdata-on  sdc1_dataGdata-off  sdc1_dataGrclk-on  sdc1_rclk+rclk-off  sdc1_rclk+sdc2-clk-on  sdc2_clk sdc2-clk-off  sdc2_clksdc2-cmd-on  sdc2_cmdG sdc2-cmd-off  sdc2_cmdG sdc2-data-on  sdc2_dataG sdc2-data-off  sdc2_dataG!timer2arm,armv8-timer0vph-pwr-regulator2regulator-fixedTvph_pwrc6{6aliases/soc/serial@f991e000 interrupt-parent#address-cells#size-cellsmodelcompatibleqcom,msm-idqcom,pmic-idqcom,board-idstdout-path#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodnext-level-cachecache-levelcpusyscon#hwlock-cellsinterruptsrangesno-mapqcom,client-idqcom,ipcqcom,smd-edgeqcom,local-pidqcom,remote-pidqcom,smd-channels#power-domain-cellsoperating-points-v2opp-levelmemory-regionqcom,rpm-msg-ramhwlocksqcom,smemqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cells#mbox-cellsframe-numberstatusclocksclock-namesassigned-clocksassigned-clock-ratespower-domainsqcom,select-utmi-as-pipe-clksnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirkmaximum-speeddr_modereg-namesinterrupt-namespinctrl-namespinctrl-0pinctrl-1bus-widthnon-removablecd-gpios#dma-cellsqcom,eeqcom,controlled-remotelynum-channelsqcom,num-eesdmasdma-namesspi-max-frequency#reset-cellsqcom,channelgpio-controllergpio-ranges#gpio-cellsgpio-reserved-rangesfunctionpinsdrive-strengthbias-disablebias-pull-downinput-enablebias-pull-upregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onserial0