A 834( 21google,tomato-rev2google,tomatomediatek,mt8195 +7Acer Tomato (rev2) boardaliases=/soc/dp-intf@1c015000F/soc/dp-intf@1c113000O/soc/mailbox@10320000T/soc/mailbox@10330000Y/soc/hdr-engine@1c114000`/soc/mutex@1c016000g/soc/mutex@1c101000n/soc/vpp-merge@1c10c000u/soc/vpp-merge@1c10d000|/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000/soc/i2c@11e02000/soc/i2c@11e03000/soc/i2c@11e04000/soc/i2c@11d00000/soc/i2c@11d02000 /soc/mmc@11230000/soc/mmc@11240000/soc/serial@11001100cpus+cpu@0cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@100cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@200cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@300cpuarm,cortex-a55*.psci<Pec3@`4s@@ cpu@400cpuarm,cortex-a78*.psci<Pf`s@@ cpu@500cpuarm,cortex-a78*.psci<Pf`s@@cpu@600cpuarm,cortex-a78*.psci<Pf`s@@cpu@700cpuarm,cortex-a78*.psci<Pf`s@@cpu-mapcluster0core0 core1 core2 core3 core4 core5core6core7idle-statespscicpu-retention-larm,idle-state+<2M_]Dcpu-retention-barm,idle-state+<-M]cpu-off-larm,idle-state+<7M]Hcpu-off-barm,idle-state+<2M]l2-cache0cachen@zl2-cache1cachen@zl3-cachecachen @zdsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default%mediatek,mt8195_mt6359_rt1019_rt56827mt8195_r1019_5682fixed-factor-clock-13mfixed-factor-clock$/clk13m+oscillator-26m fixed-clockP/clk26moscillator-32k fixed-clockP/clk32kperformance-controller@11bc10mediatek,cpufreq-hw * 0 Bopp-table-gpuoperating-points-v2\topp-390000000g>n hopp-410000000gpn opp-431000000gn opp-473000000g1h@n <opp-515000000gFn <opp-556000000g!#n Ҧopp-598000000g#n opp-640000000g&%n opp-670000000g'cn opp-700000000g)'n Lopp-730000000g+n }opp-760000000g-Ln `opp-790000000g/qn 4opp-820000000g05n opp-850000000g2n @opp-880000000g4sn qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.05smctimerarm,armv8-timer @   soc+ simple-bus|interrupt-controller@c000000 arm,gic-v3  *    ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensyscon*syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd*syscon@10003000mediatek,mt8195-pericfgsyscon*0@pinctrl@10005000mediatek,mt8195-pinctrl*PBiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint '3default>WI2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDgEFGHIJK<12345pins-hp-jack-int-odlgYn{ecr50-irq-default-pinscpins-gsc-ap-int-odlgXncros-ec-irq-default-pins7pins-ec-ap-int-odlg{enedptx-default-pinspins-cmd-datg{disp-pwm0-default-pins:pins-disp-pwmgRadptx-default-pinspins-cmd-datg{i2c0-default-pinsZpins-busg i2c1-default-pins[pins-busg  {i2c2-default-pins^pins-busg  i2c3-default-pinsbpins-busg{i2c4-default-pinsdpins-busg{i2c5-default-pinsVpins-busgi2c7-default-pinsWpins-busgmmc0-default-pinsCpins-cmd-dat$g~}|{wvutyn{epins-clkgzfpins-rstgx{emmc0-uhs-pinsDpins-cmd-dat$g~}|{wvutyn{epins-clkgzfpins-dsgfpins-rstgx{emmc1-detect-pinsHpins-insertg6{mmc1-default-pinsGpins-cmd-datgnpqrsn{epins-clkgofnor-default-pinsTpins-ck-io gpins-csg{pcie0-default-pinspins-bus g{pcie1-default-pinsSpins-bus g{pio-default-pinspins-wifi-enableg:pins-low-power-pd,g./0ABCDnpins-low-power-pupd<gMNOPSUZ[]^_`hiknepins-low-power-hdmi-disableg !"#npins-low-power-pcie0-disable gnrt1019p-default-pinspins-amp-sdbgdscp-default-pins-pins-vreqgLnspi0-default-pins6pins-cs-mosi-clk gpins-misogsubpmic-default-pinsXpins-subpmic-int-ngn{trackpad-default-pins\pins-int-ngn{touchscreen-default-pinsepins-int-ng\n{epins-rstg8pins-report-swg9syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd*`power-controller!mediatek,mt8195-power-controller+/power-domain@8*+power-domain@9* mfgalt+power-domain@10* power-domain@11* power-domain@12* power-domain@13* power-domain@14*power-domain@15* @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24*vdec1-0power-domain@27* venc1-larbpower-domain@16*8 $ % & ' ( )Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17*!!vppsys1vppsys1-0vppsys1-1power-domain@22* """"$wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23*#vdec0-0power-domain@25*$vdec2-0power-domain@26*% venc0-larbpower-domain@18* &&&&vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19*power-domain@20*power-domain@21*Qhdmi_txpower-domain@28*''  img-0img-1+power-domain@29*power-domain@30*'(ipeipe-0ipe-1power-domain@31*()))))cam-0cam-1cam-2cam-3cam-4+power-domain@32* power-domain@33*!power-domain@34*"power-domain@0*power-domain@1*power-domain@2*power-domain@3*power-domain@4*57csi_rx_topcsi_rx_top1power-domain@5** etherpower-domain@6*Xn adspadsp1+power-domain@7* g"n2audioaudio1audio2audio3watchdog@10007000mediatek,mt8195-wdt*p4syscon@1000c000"mediatek,mt8195-apmixedsyssyscon*timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer*p +pwrap@10024000mediatek,mt8195-pwrapsyscon*@pwrap spiwrap,$<pmicmediatek,mt6359 Smt6359codecgzregulatorsbuck_vs1vs1 5!buck_vgpu11vgpu117 buck_vmodemvmodem*buck_vpuvpu7 buck_vcorevcore  buck_vs2vs2 5jbuck_vpavpa 7,buck_vproc2vproc27L buck_vproc1vproc17L buck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshubdpdpldo_vaud18vaud18w@w@ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 ldo_vusbvusb--Aldo_vsram_proc2 vsram_proc2 Lldo_vio18vio18_ldo_vcamiovcamioldo_vcn18vcn18w@w@ldo_vfe28vfe28**xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@ldo_vsram_others vsram_others q qldo_vefusevefuseldo_vxo22vxo22w@!ldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**ldo_vio28vio28*2Zldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2ZEldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O ldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md *ldo_vufsvufsFldo_vm18vm18ldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 Lldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi *p pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux,$<+mt6315@6mediatek,mt6315-regulator*regulatorsvbuck1*vbuck1Vbcpu7j mt6315@7mediatek,mt6315-regulator*regulatorsvbuck1*vbuck1Vgpu h7j uinfra-iommu@10315000mediatek,mt8195-iommu-infra*1PPP?Nmailbox@10320000mediatek,mt8195-gce*2@Lmailbox@10330000mediatek,mt8195-gce*3@Lvscp@10500000mediatek,mt8195-scp0*Prpsramcfgl1tcmokayXmediatek/mt8195/scp.imgf,default-cros-ec-rpmsggoogle,cros-ec-rpmsgtcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adsp*r.dsp@10803000mediatek,mt8195-dsp *0 cfgsram,Xn.#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h/rxtx01okayf23mailbox@10816000mediatek,mt8195-adsp-mboxL*`0mailbox@10817000mediatek,mt8195-adsp-mboxL*p1mt8195-afe-pcm@10890000mediatek,mt8195-audio*/64 audiosysg"#neabcd2.clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokayf5serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart*  baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc* main disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon*0*spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+*parent-clksel-clkspi-clkokaydefault6 ec@0+google,cros-ec-spi* Sdefault74-keyboard-backlightgoogle,cros-kbd-led-backlighti2c-tunnelgoogle,cros-ec-i2c-tunnelF+sbs-battery@bsbs,sbs-battery* Xlregulator@0google,cros-ec-regulator*mt_pmic_vmc_ldoO6Jregulator@1google,cros-ec-regulator*mt_pmic_vmch_ldo)26Itypecgoogle,cros-ec-typec+connector@0usb-c-connector*dualhostsourceconnector@1usb-c-connector*dualhostsourcekeyboard-controllergoogle,cros-ec-keyb Dtxc q rs}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i(  thermal-sensor@1100b000mediatek,mt8195-lvts-ap*89$lvts-calib-data-1lvts-calib-data-2!pwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm*/7*0mainmmokaydefault:pwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm*7+Nmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+*3parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+* 4parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+*05parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+*<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+*=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave*Rspi,< disabledspi@1101e000mediatek,mt8195-spi-slave*Sspi,< disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a*@Bmacirq.axiapbmac_mainptp_refrmii_internalmac_cg0**RST* ,RST</Rc;s<= disabledmdiosnps,dwmac-mdio+stmmac-axi-config;rx-queues-config<queue0  queue1  queue2  queue3  tx-queues-config 8 N=queue0 `  lqueue1 `  lqueue2 `  lqueue3 `  lusb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci *  > macippc z>?,,-<$/B$sys_ckref_ckmcu_ckdma_ckxhci_ck @g okay A Bmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc *#sourcehclksource_cgokay    L8      &defaultstate_uhsC 4D >E JFmmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc *$$sourcehclksource_cg,<okay  W h68  q defaultstate_uhsGH 4G x  >I JJmmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc *% Isourcehclksource_cg, < disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu*'89$lvts-calib-data-1lvts-calib-data-2!usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci *))> macippc zK,./<$**$sys_ckref_ckmcu_ckdma_ckxhci_ck @h okay A Busb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci ***> macippc zL,01< **$sys_ckref_ckmcu_ckdma_ckxhci_ck @i okay A Busb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci *++> macippc zM,23< ** $sys_ckref_ckmcu_ckdma_ckxhci_ck @j okay  A Bpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@ pcie-mac 8|  N 0V#&+K*/pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem,G< zO pcie-phy/mac ` PPPP disabledinterrupt-controllerPpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pciepci+*/@ pcie-mac 8|$$ $ $  N (WXQ*/pl_250mtl_26mtl_96mtl_32kperi_26mperi_mem,H< zQ pcie-phy/mac ` RRRRokaydefaultSinterrupt-controllerRspi@1132c000(mediatek,mt8195-normediatek,mt8173-nor*29o** spisfaxi+okaydefaultTflash@0jedec,spi-nor*4u  efuse@11c10000%mediatek,mt8195-efusemediatek,efuse*+usb3-tx-imp@184,1* kusb3-rx-imp@184,2* jusb3-intr@185* iusb3-tx-imp@186,1* husb3-rx-imp@186,2* gusb3-intr@187* fusb2-intr-p0@188,1* usb2-intr-p1@188,2* usb2-intr-p2@189,1* usb2-intr-p3@189,2* pciephy-rx-ln1@190,1* rpciephy-tx-ln1-nmos@190,2* qpciephy-tx-ln1-pmos@191,1* ppciephy-rx-ln0@191,2* opciephy-tx-ln0-nmos@192,1* npciephy-tx-ln0-pmos@192,2* mpciephy-glb-intr@193* ldp-data@1ac*lvts1-calib@1bc*8lvts2-calib@1d0*89t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+|okayusb-phy@0*ref Lt-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+|okayusb-phy@0*ref Mi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"U; maindma+okayPdefaultVi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"U; maindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "U; maindma+okayPdefaultWpmic@34mediatek,mt6360*4 SBIRQBdefaultX clock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s*0Ui2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"Y; maindma+okayPdefaultZi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c *"Y; maindma+okayP $0default[trackpad@15elan,ekth3000* Sdefault\ >] i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c * "Y; maindma+okayPdefault^codec@1a* SY I X_ d` rarealtek,rt5682i ~i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c *0"Y; maindma+okayPdefaultbtpm@50 google,cr50*P SXdefaultci2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c *@"Y; maindma+okayPdefaultdtouchscreen@10 hid-over-i2c*  S\defaulte  ]okayclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w*PYt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+|/okayusb-phy@0*  refda_ref Kusb-phy@700* refda_ref fghintrrx_imptx_imp Qt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+|okayusb-phy@0*  refda_ref >usb-phy@700* refda_ref ijkintrrx_imptx_imp ?phy@11e80000mediatek,mt8195-pcie-phy*siflmnopqrGglb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln1/  disabledOufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy* unipromp  disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm*@s0 Bjobmmugpu t(/ / / / / core0core1core2core3core4okay uclock-controller@13fbf000mediatek,mt8195-mfgcfg*ssyscon@14000000mediatek,mt8195-vppsys0syscon*mutex@1400f000mediatek,mt8195-vpp-mutex*P v/smi@14010000mediatek,mt8195-smi-sub-common*apbsmigals0 w/xsmi@14011000mediatek,mt8195-smi-sub-common*apbsmigals0 w/smi@14012000mediatek,mt8195-smi-common-vpp*  apbsmigals0gals1/wlarb@14013000mediatek,mt8195-smi-larb*0  xapbsmi/{iommu@14018000mediatek,mt8195-iommu-vpp*8 -yz{|}~Rbclk?/clock-controller@14e00000mediatek,mt8195-wpesys*"clock-controller@14e02000mediatek,mt8195-wpesys_vpp0* clock-controller@14e03000mediatek,mt8195-wpesys_vpp1*0larb@14e04000mediatek,mt8195-smi-larb*@  ""apbsmi/larb@14e05000mediatek,mt8195-smi-larb*P  w"" apbsmigals/}syscon@14f00000mediatek,mt8195-vppsys1syscon*!mutex@14f01000mediatek,mt8195-vpp-mutex*{ v !'/larb@14f02000mediatek,mt8195-smi-larb*   !! apbsmigals/larb@14f03000mediatek,mt8195-smi-larb*0  x!! apbsmigals/|clock-controller@15000000mediatek,mt8195-imgsys*'larb@15001000mediatek,mt8195-smi-larb*   '''  apbsmigals/smi@15002000mediatek,mt8195-smi-sub-common* ''apbsmigals0 w/smi@15003000mediatek,mt8195-smi-sub-common*0''' apbsmigals0 /clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top*larb@15120000mediatek,mt8195-smi-larb*   'apbsmi/clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr*clock-controller@15220000mediatek,mt8195-imgsys1_wpe*"larb@15230000mediatek,mt8195-smi-larb*#   'apbsmi/clock-controller@15330000mediatek,mt8195-ipesys*3(larb@15340000mediatek,mt8195-smi-larb*4   ((apbsmi/~clock-controller@16000000mediatek,mt8195-camsys*)larb@16001000mediatek,mt8195-smi-larb*   ))) apbsmigals/larb@16002000mediatek,mt8195-smi-larb*   ))apbsmi/smi@16004000mediatek,mt8195-smi-sub-common*@)))apbsmigals0 /smi@16005000mediatek,mt8195-smi-sub-common*P))apbsmigals0 w/larb@16012000mediatek,mt8195-smi-larb*   apbsmi/ larb@16013000mediatek,mt8195-smi-larb*0  apbsmi/ larb@16014000mediatek,mt8195-smi-larb*@  apbsmi/!larb@16015000mediatek,mt8195-smi-larb*P  apbsmi/!clock-controller@1604f000mediatek,mt8195-camsys_rawa*clock-controller@1606f000mediatek,mt8195-camsys_yuva*clock-controller@1608f000mediatek,mt8195-camsys_rawb*clock-controller@160af000mediatek,mt8195-camsys_yuvb* clock-controller@16140000mediatek,mt8195-camsys_mraw*larb@16141000mediatek,mt8195-smi-larb*  )) apbsmigals/"larb@16142000mediatek,mt8195-smi-larb*   apbsmi/"clock-controller@17200000mediatek,mt8195-ccusys* larb@17201000mediatek,mt8195-smi-larb*   apbsmi/video-codec@18000000mediatek,mt8195-vcodec-dec < I+ *@|`video-codec@2000mediatek,mtk-vcodec-lat-soc*  I A##selvdeclattop,A</video-codec@10000mediatek,mtk-vcodec-lat*0 I A##selvdeclattop,A</video-codec@25000mediatek,mtk-vcodec-core*PP I Aselvdeclattop,A</larb@1800d000mediatek,mt8195-smi-larb*  ##apbsmi/larb@1800e000mediatek,mt8195-smi-larb*  #apbsmi/clock-controller@1800f000mediatek,mt8195-vdecsys_soc*#larb@1802e000mediatek,mt8195-smi-larb*  apbsmi/clock-controller@1802f000mediatek,mt8195-vdecsys*larb@1803e000mediatek,mt8195-smi-larb*  $apbsmi/clock-controller@1803f000mediatek,mt8195-vdecsys_core1*$clock-controller@190f3000mediatek,mt8195-apusys_pll*0clock-controller@1a000000mediatek,mt8195-vencsys*%larb@1a010000mediatek,mt8195-smi-larb*  %%apbsmi/video-codec@1a020000mediatek,mt8195-vcodec-enc*H I`abcdvwxyU <% venc_sel,@</+jpgdec-mastermediatek,mt8195-jpgdec/0 Imnrstu+|jpgdec@1a040000mediatek,mt8195-jpgdec-hw*0 ImnrstuW%jpgdec/jpgdec@1a050000mediatek,mt8195-jpgdec-hw*0 ImnrstuX%jpgdec/jpgdec@1b040000mediatek,mt8195-jpgdec-hw*0 I\jpgdec/clock-controller@1b000000mediatek,mt8195-vencsys_core1*syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon*  jpgenc-mastermediatek,mt8195-jpgenc/ I+|jpgenc@1a030000mediatek,mt8195-jpgenc-hw* IghilV%jpgenc/jpgenc@1b030000mediatek,mt8195-jpgenc-hw* I[jpgenc/larb@1b010000mediatek,mt8195-smi-larb*  w  apbsmigals/ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl*|/  I rdma@1c002000mediatek,mt8195-disp-rdma* ~/  I  color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color*0/  0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr*@/  @aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal*P/  Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma*`/  `dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither*p/  pdsc@1c009000mediatek,mt8195-disp-dsc*/  merge@1c014000mediatek,mt8195-disp-merge*@/  @dp-intf@1c015000mediatek,mt8195-dp-intf*P  ,enginepixelpllokayportendpoint Pmutex@1c016000mediatek,mt8195-disp-mutex*`/  `Ularb@1c018000mediatek,mt8195-smi-larb*   ( (  apbsmigals/larb@1c019000mediatek,mt8195-smi-larb*  w (  apbsmigals/ysyscon@1c100000mediatek,mt8195-vdosys1syscon*  &smi@1c01b000mediatek,mt8195-smi-common-vdo*  % & ) $apbsmigals0gals1/iommu@1c01f000mediatek,mt8195-iommu-vdo*8 -? 'bclk/mutex@1c101000mediatek,mt8195-disp-mutex* vdo1_mutex/& vdo1_mutex `larb@1c102000mediatek,mt8195-smi-larb*   &&& apbsmigals/larb@1c103000mediatek,mt8195-smi-larb*0  w&&  apbsmigals/zdma-controller@1c104000mediatek,mt8195-vdo1-rdma*@&/ I@ @ tdma-controller@1c105000mediatek,mt8195-vdo1-rdma*P&/ I` P tdma-controller@1c106000mediatek,mt8195-vdo1-rdma*`&/ IA ` tdma-controller@1c107000mediatek,mt8195-vdo1-rdma*p&/ Ia p tdma-controller@1c108000mediatek,mt8195-vdo1-rdma*&/ IB  tdma-controller@1c109000mediatek,mt8195-vdo1-rdma*&/ Ib  tdma-controller@1c10a000mediatek,mt8195-vdo1-rdma*&/ IC  tdma-controller@1c10b000mediatek,mt8195-vdo1-rdma*&/ Ic  tvpp-merge@1c10c000mediatek,mt8195-disp-merge*& &mergemerge_async/  &vpp-merge@1c10d000mediatek,mt8195-disp-merge*& &mergemerge_async/  &vpp-merge@1c10e000mediatek,mt8195-disp-merge*& &mergemerge_async/  &vpp-merge@1c10f000mediatek,mt8195-disp-merge*& &mergemerge_async/  &vpp-merge@1c110000mediatek,mt8195-disp-merge*& &mergemerge_async/  &dp-intf@1c113000mediatek,mt8195-dp-intf*0/&&/enginepixelpllokayportendpoint Phdr-engine@1c114000mediatek,mt8195-disp-ethdrp*@Pp4mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pph&%& &#&!&$&"&1&&&'&(&)&*mixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top/ Ide(&3&4&5&6&7Evdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx*Pdp_calibration_data/ okaydefaultports+port@0*endpoint Pport@1*endpoint dp-tx@1c600000mediatek,mt8195-dp-tx*`dp_calibration_data/ okaydefaultports+port@0*endpoint Pport@1*endpoint thermal-zonescpu0-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu1-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu2-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu3-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu4-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu5-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu6-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  cpu7-thermal   tripstrip-alert L %passivetrip-crit   %criticalcooling-mapsmap0 0  vpu0-thermal   tripstrip-alert L %passivetrip-crit   %criticalvpu1-thermal   tripstrip-alert L %passivetrip-crit   %criticalgpu0-thermal   tripstrip-alert L %passivetrip-crit   %criticalgpu1-thermal   tripstrip-alert L %passivetrip-crit   %criticalvdec-thermal   tripstrip-alert L %passivetrip-crit   %criticalimg-thermal   tripstrip-alert L %passivetrip-crit   %criticalinfra-thermal   tripstrip-alert L %passivetrip-crit   %criticalcam0-thermal   tripstrip-alert L %passivetrip-crit   %criticalcam1-thermal   tripstrip-alert L %passivetrip-crit   %criticalbacklight-lcd0pwm-backlight % 7@ PR ] t  ychosen serial0:115200n8memory@40000000memory*@regulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5 2Z2Z aregulator-pp3300-s3regulator-fixed pp3300_s3 2Z2Z `]regulator-pp3300-z2regulator-fixed pp3300_z2 2Z2Z `regulator-pp4200-z2regulator-fixed pp4200_z2 @@@@ regulator-pp5000-s5regulator-fixed pp5000_s5 LK@LK@ regulator-ppvar-sysregulator-fixed ppvar_sys regulator-5v0-usb-vbusregulator-fixed usb-vbusLK@LK@ Breserved-memory+|memory@50000000shared-dma-pool*P ,memory@60000000shared-dma-pool*` 3memory@60d80000shared-dma-pool*` 5memory@60e80000shared-dma-pool*`( 2rt1019prealtek,rt1019p rt1019pdefault d compatibleinterrupt-parent#address-cells#size-cellsmodeldp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-source#io-channel-cellsmediatek,pad-selectspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsi2c-scl-internal-delay-nsvcc-supplyrealtek,jd-srcAVDD-supplyMICVDD-supplyVBAT-supplyrealtek,btndet-delayhid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,smimediatek,larb-idmediatek,larbsmediatek,scpiommusremote-endpointmediatek,gce-events#dma-cellsmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmspower-supplystdout-pathregulator-boot-onvin-supplyenable-active-highno-maplabelsdb-gpios