683`(K3($mediatek,mt6795-evbmediatek,mt6795 +!7MediaTek MT6795 Evaluation Board =embeddedpsci arm,psci-0.2Jsmccpus+cpu@0Qcpuarm,cortex-a53]pscikocpu@1Qcpuarm,cortex-a53]psciko@@cpu@2Qcpuarm,cortex-a53]psciko@@cpu@3Qcpuarm,cortex-a53]psciko@@ cpu@100Qcpuarm,cortex-a53]psciko@@ cpu@101Qcpuarm,cortex-a53]psciko@@ cpu@102Qcpuarm,cortex-a53]psciko@@ cpu@103Qcpuarm,cortex-a53]psciko@@ cpu-mapcluster0core0core1core2core3 cluster1core0 core1 core2 core3 l2-cache0cache@l2-cache1cache@oscillator-26m fixed-clock,clk26moscillator-32k fixed-clock},clk32kdummy13m fixed-clock]@pmuarm,cortex-a53-pmu0?   J timerarm,armv8-timer 0?   soc+ simple-bus]syscon@10000000 mediatek,mt6795-topckgensysconksyscon@10001000 mediatek,mt6795-infracfgsysconkdsyscon@10003000mediatek,mt6795-pericfgsysconk0dsyscon@10006000sysconsimple-mfdk`qpower-controller!mediatek,mt6795-power-controller+qpower-domain@1kRmmqpower-domain@2kRUmmvencqpower-domain@3kRmmqpower-domain@0kRmmqpower-domain@4kRemmmjcqpower-domain@5kqpower-domain@6kmfg+qpower-domain@7k+qpower-domain@8kqpinctrl@10005000mediatek,mt6795-pinctrl kP baseeint?watchdog@10007000mediatek,mt6795-wdtkp ?dtimer@10008000,mediatek,mt6795-timermediatek,mt6577-timerk ?pwrap@1000d000mediatek,mt6795-pwrapkpwrap ?pwrap c spiwrapintpol-controller@10200620.mediatek,mt6795-sysirqmediatek,mt6577-sysirq k  timer@10200670mediatek,mt6795-systimerk p ?@clk13miommu@10205000mediatek,mt6795-m4uk Pbclk ?!0>syscon@10209000"mediatek,mt6795-apmixedsyssysconk clock-controller@10209f00mediatek,mt6795-fhctlk  Kdisabledmailbox@10212000(mediatek,mt6795-gcemediatek,mt8173-gcek!  ?gceRinterrupt-controller@10221000 arm,gic-400 @k"" "@ "`  ? cci@10390000 arm,cci-400+k9]9slave-if@1000arm,cci-400-ctrl-if ^ace-litekslave-if@4000arm,cci-400-ctrl-if^acek@slave-if@5000arm,cci-400-ctrl-if^acekPpmu@9000arm,cci-400-pmu,r1kP<?:;<=>serial@11002000*mediatek,mt6795-uartmediatek,mt6577-uartk  ?[ baudbusmrtxrxKokayserial@11003000*mediatek,mt6795-uartmediatek,mt6577-uartk0 ?\ baudbusmrtxrx Kdisableddma-controller@110003802mediatek,mt6795-uart-dmamediatek,mt6577-uart-dmak`````````?ghijklmn| apdmaserial@11004000*mediatek,mt6795-uartmediatek,mt6577-uartk@ ?]  baudbusmrtxrx Kdisabledserial@11005000*mediatek,mt6795-uartmediatek,mt6577-uartkP ?^! baudbusmrtxrx Kdisabledpwm@11006000mediatek,mt6795-pwmk` ?MHS ,topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7 Kdisabledi2c@11007000(mediatek,mt6795-i2cmediatek,mt8173-i2c kpp ?T  maindma+ Kdisabledi2c@11008000(mediatek,mt6795-i2cmediatek,mt8173-i2c kp ?U  maindma+ Kdisabledi2c@11009000(mediatek,mt6795-i2cmediatek,mt8173-i2c kp ?V  maindma+ Kdisabledi2c@11010000(mediatek,mt6795-i2cmediatek,mt8173-i2c kp ?W  maindma+ Kdisabledi2c@11011000(mediatek,mt6795-i2cmediatek,mt8173-i2c kp ?X  maindma+ Kdisabledmmc@11230000mediatek,mt6795-mmck# ?O \]sourcehclksource_cg Kdisabledmmc@11240000mediatek,mt6795-mmck$ ?PO sourcehclk Kdisabledmmc@11250000mediatek,mt6795-mmck% ?QO sourcehclk Kdisabledmmc@11260000mediatek,mt6795-mmck& ?RO sourcehclk Kdisabledsyscon@14000000mediatek,mt6795-mmsyssysconk0Rׄdlarb@14021000mediatek,mt6795-smi-larbkapbsmi0smi@14022000mediatek,mt6795-smi-commonk 0apbsmilarb@15001000mediatek,mt6795-smi-larbkapbsmi0clock-controller@16000000mediatek,mt6795-vdecsysklarb@16010000mediatek,mt6795-smi-larbkapbsmi0clock-controller@18000000mediatek,mt6795-vencsysk larb@18001000mediatek,mt6795-smi-larbk  apbsmi0aliases/soc/serial@11002000'/soc/serial@11003000//soc/serial@110040007/soc/serial@11005000memory@40000000Qmemoryk@chosen?serial0:921600n8 compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typemethoddevice_typeenable-methodregcci-control-portnext-level-cachephandlei-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setscpucache-levelcache-unified#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinityranges#reset-cells#power-domain-cellsclocksclock-namesmediatek,infracfgreg-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cellstimeout-secresetsreset-namesmediatek,larbspower-domains#iommu-cellsstatus#mbox-cellsinterface-typedmasdma-namesdma-requestsmediatek,dma-33bits#dma-cells#pwm-cellsclock-divassigned-clocksassigned-clock-ratesmboxesmediatek,gce-client-regmediatek,smimediatek,larb-idserial0serial1serial2serial3stdout-path