From: Manfred Spraul <manfred@colorfullife.com>

the attached patch switches the SLAB_HWCACHE_ALIGN alignment from the
compile time L1 cache line size to the runtime detected value for i386. 
x86-64 already uses the runtime detection.


---

 25-akpm/include/asm-i386/processor.h |    2 ++
 1 files changed, 2 insertions(+)

diff -puN include/asm-i386/processor.h~enable-runtime-cache-line-size-for-slab-on-i386 include/asm-i386/processor.h
--- 25/include/asm-i386/processor.h~enable-runtime-cache-line-size-for-slab-on-i386	2004-05-17 23:30:09.084774448 -0700
+++ 25-akpm/include/asm-i386/processor.h	2004-05-17 23:30:09.087773992 -0700
@@ -643,6 +643,8 @@ extern inline void prefetchw(const void 
 
 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 
+#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
+
 #ifdef CONFIG_SCHED_SMT
 #define ARCH_HAS_SCHED_DOMAIN
 #define ARCH_HAS_SCHED_WAKE_IDLE

_