diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/gdb/config/h8300/tm-h8300.h gdb-5.3-h8/gdb/config/h8300/tm-h8300.h --- gdb-5.3/gdb/config/h8300/tm-h8300.h 2003-09-06 23:13:50.000000000 +0900 +++ gdb-5.3-h8/gdb/config/h8300/tm-h8300.h 2003-12-10 22:57:55.000000000 +0900 @@ -36,6 +36,7 @@ GDB_TARGET_IS_H8300 in remote-e7000.c */ extern int h8300hmode; extern int h8300smode; +extern int int32mode; /* Number of bytes in a word */ @@ -59,9 +60,11 @@ extern void h8300_init_extra_frame_info (); #undef TARGET_INT_BIT -#define TARGET_INT_BIT 16 +#define TARGET_INT_BIT (int32mode ? 32:16) #undef TARGET_LONG_BIT #define TARGET_LONG_BIT 32 +#undef TARGET_LONG_LONG_BIT +#define TARGET_LONG_LONG_BIT (int32mode ? 64:32) #undef TARGET_PTR_BIT #define TARGET_PTR_BIT (h8300hmode ? 32:16) @@ -88,8 +91,7 @@ #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) -/*#define BREAKPOINT {0x7A, 0xFF} */ -#define BREAKPOINT {0x01, 0x80} /* Sleep */ +#define BREAKPOINT {0x7A, 0xFF} #define REMOTE_BREAKPOINT { 0x57, 0x30} /* trapa #3 */ /* If your kernel resets the pc after the trap happens you may need to define this before including this file. */ diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/gdb/h8300-tdep.c gdb-5.3-h8/gdb/h8300-tdep.c --- gdb-5.3/gdb/h8300-tdep.c 2003-09-06 23:14:05.000000000 +0900 +++ gdb-5.3-h8/gdb/h8300-tdep.c 2004-01-23 22:28:12.000000000 +0900 @@ -775,6 +775,23 @@ help_list (setmemorylist, "set memory ", -1, gdb_stdout); } +static void set_intsize(char *args, int from_tty) +{ + int size = 0; + if (args) + size = atoi(args); + switch (size) { + case 16: + int32mode = 0; + break ; + case 32: + int32mode = 1; + break ; + default: + printf_unfiltered ("\"set intsize\" must be followed by 16 or 32"); + } +} + /* set_machine_hook is called as the exec file is being opened, but before the symbol file is opened. This allows us to set the h8300hmode flag based on the machine type specified in the exec @@ -818,6 +835,9 @@ add_cmd ("h8300s", class_support, h8300s_command, "Set machine to be H8/300S.", &setmemorylist); + add_cmd ("intsize", no_class, set_intsize, + "set the int size",&setlist); + /* Add a hook to set the machine type when we're loading a file. */ specify_exec_file_hook (set_machine_hook); diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/sim/h8300/Makefile.in gdb-5.3-h8/sim/h8300/Makefile.in --- gdb-5.3/sim/h8300/Makefile.in 2003-09-06 23:14:55.000000000 +0900 +++ gdb-5.3-h8/sim/h8300/Makefile.in 2003-09-06 23:13:04.000000000 +0900 @@ -18,7 +18,7 @@ ## COMMON_PRE_CONFIG_FRAG -SIM_OBJS = compile.o sim-load.o +SIM_OBJS = compile.o sim-load.o io.o ## COMMON_POST_CONFIG_FRAG compile.o: compile.c inst.h config.h \ diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/sim/h8300/compile.c gdb-5.3-h8/sim/h8300/compile.c --- gdb-5.3/sim/h8300/compile.c 2003-09-06 23:14:55.000000000 +0900 +++ gdb-5.3-h8/sim/h8300/compile.c 2004-02-03 20:50:35.000000000 +0900 @@ -120,6 +120,7 @@ int h8300hmode = 0; int h8300smode = 0; +int int32mode = 0; static int memory_size; @@ -334,6 +335,10 @@ bit = thisnib; } + else if (looking_for & IMM2) + { + plen = 1; + } else if (looking_for == E) { dst->op = q; @@ -929,7 +934,7 @@ int m; \ int b; \ if (f) ea = fetch (&code->dst); \ - m=1<< fetch (&code->src); \ + m=1<< (fetch (&code->src) & 7); \ op; \ if (s) store (&code->dst,ea); goto next; \ } @@ -984,6 +989,8 @@ int c, nz, v, n, u, h, ui, intMaskBit; int trace, intMask; int oldmask; + int vector; + init_pointers (); prev = signal (SIGINT, control_c); @@ -1044,6 +1051,26 @@ #endif + if ((vector=iosimulation(&cpu,cycles)) && ((cpu.ccr & 0x80) == 0)) + { + BUILDSR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + if (h8300smode) { + int exr; + BUILDEXR(); + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + cpu.exr |= 0x07; + intMask = 0x07; + } + cpu.ccr|=0x80; + intMaskBit = 1; + goto top; + } + if (code->opcode) { cycles += code->cycles; @@ -1483,6 +1510,7 @@ cpu.exception = SIGILL; goto end; case O (O_SLEEP, SN): +#if 0 /* FIXME: Doesn't this break for breakpoints when r0 contains just the right (er, wrong) value? */ cpu.state = SIM_STATE_STOPPED; @@ -1494,6 +1522,33 @@ cpu.exception = SIGILL; else cpu.exception = SIGTRAP; +#endif + if ((cpu.ccr & 0x80) != 0) + { + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGTRAP; + } else + while (cpu.state = SIM_STATE_RUNNING) { + if ((vector=iosimulation(&cpu,cycles)) && !(cpu.ccr & 0x80)) + { + usleep(100); + BUILDSR(); + BUILDEXR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|pc+2); + pc=GET_MEMORY_L(vector*(h8300hmode?4:2)); + if (h8300smode) { + int exr; + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + intMask = 0x07; + } + intMaskBit = 1; + goto top; + } + cycles++; + } goto end; case O (O_BPT, SN): cpu.state = SIM_STATE_STOPPED; @@ -1671,6 +1726,44 @@ } } goto next; + case O (O_RTE, SN): + { + unsigned int frame; + if (h8300smode) { + unsigned int exr; + exr = GET_MEMORY_W (cpu.regs[7]); + exr >>= 8; + exr &= 0xff; + cpu.exr = exr; + cpu.regs[7]+=2; + } + frame = GET_MEMORY_L (cpu.regs[7]); + cpu.ccr=frame>>24; + GETSR(); + GETEXR(); + pc=frame & 0xffffff; + cpu.regs[7]+=4; + }; + goto end; + case O (O_TRAPA, SB): + { + int v; + v=GET_MEMORY_W(pc)>>4; + v&=3; + BUILDSR(); + BUILDEXR(); + cpu.regs[7]-=4; + SET_MEMORY_L(cpu.regs[7],(cpu.ccr<<24)|code->next_pc); + pc=GET_MEMORY_L(v*(h8300hmode?4:2)+0x08*(h8300hmode?4:2)); + intMaskBit = 1; + if (h8300smode) { + int exr; + exr = cpu.exr << 8 | cpu.exr; + cpu.regs[7]-=2; + SET_MEMORY_W(cpu.regs[7],exr); + } + }; + goto end; default: illegal: @@ -2160,10 +2253,15 @@ char **argv; { /* FIXME: Much of the code in sim_load can be moved here. */ + char *ptyname; sim_kind = kind; myname = argv[0]; sim_callback = ptr; + if((ptyname=openpty())!=NULL) + (*sim_callback->printf_filtered) (sim_callback, + "SCI0 = %s\n",ptyname); + /* Fudge our descriptor. */ return (SIM_DESC) 1; } @@ -2174,6 +2272,7 @@ int quitting; { /* Nothing to do. */ + closepty(); } /* Called by gdb to load a program into memory. */ @@ -2247,6 +2346,7 @@ abort (); cpu.mask = memory_size - 1; + init_ioregs(&cpu); if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, sim_kind == SIM_OPEN_DEBUG, 0, sim_write) diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/sim/h8300/inst.h gdb-5.3-h8/sim/h8300/inst.h --- gdb-5.3/sim/h8300/inst.h 2003-09-06 23:14:55.000000000 +0900 +++ gdb-5.3-h8/sim/h8300/inst.h 2003-09-06 23:13:04.000000000 +0900 @@ -20,7 +20,7 @@ Next 2 macros are ugly for any workstation, but while they're work. Memory size MUST be configurable. */ -#define H8300H_MSIZE (1<<18) +#define H8300H_MSIZE (1<<24) #define H8300S_MSIZE (1<<24) #define CSIZE 1000 diff -Nru -X /home/ysato/.exclude-diff gdb-5.3/sim/h8300/io.c gdb-5.3-h8/sim/h8300/io.c --- gdb-5.3/sim/h8300/io.c 1970-01-01 09:00:00.000000000 +0900 +++ gdb-5.3-h8/sim/h8300/io.c 2003-09-06 23:13:04.000000000 +0900 @@ -0,0 +1,363 @@ +/* + H8 simulator Internal Peripheral Support +*/ + +#include +#include +#include +#include +#include + +#include "inst.h" + +#define SMR (cpu->memory[sci_base+0]) +#define BRR (cpu->memory[sci_base+1]) +#define SCR (cpu->memory[sci_base+2]) +#define TDR (cpu->memory[sci_base+3]) +#define SSR (cpu->memory[sci_base+4]) +#define RDR (cpu->memory[sci_base+5]) + +#define TCR 0 +#define TCSR 2 +#define TCORA 4 +#define TCORB 6 +#define TCNT 8 + +static int scifd=-1; +static struct termios old_attr; +static unsigned char ssr=0; +static unsigned int sci_base; + +extern int h8300hmode; +extern int h8300smode; + +static void timer8sub(const int base[], unsigned char tcsr[], int cyc, cpu_state_type *cpu, int ch) +{ + static int prescale[3]={8,64,8192}; + const int prescale_div[3]={8,64,8192}; + int tm,cnt,pcnt; + for (pcnt = 0; pcnt < 3; pcnt++) { + prescale[pcnt] -= cyc; + if (prescale[pcnt]<=0) + { + for(tm=0;tmmemory[base[tm]+TCSR] & 0xe0); + if ((cpu->memory[base[tm]+TCR]&0x07) == (pcnt+1)) + { + cnt=++cpu->memory[base[tm]+TCNT]; + if (cnt>=0x100) + { + tcsr[tm]|=0x20; + cnt=0; + } + cpu->memory[base[tm]+TCNT]=cnt; + } + if (cpu->memory[base[tm]+TCNT] >= cpu->memory[base[tm]+TCORA]) + { + tcsr[tm]|=0x40; + if ((cpu->memory[base[tm]+TCR]&0x18) == 0x08) + cpu->memory[base[tm]+TCNT] = 0; + } + if (cpu->memory[base[tm]+TCNT] >= cpu->memory[base[tm]+TCORB]) + { + tcsr[tm]|=0x80; + if ((cpu->memory[base[tm]+TCR]&0x18) == 0x10) + cpu->memory[base[tm]+TCNT] = 0; + } + cpu->memory[base[tm]+TCSR] &= 0x1f; + cpu->memory[base[tm]+TCSR] |= (tcsr[tm] & 0xe0); + } + prescale[pcnt]+=prescale_div[pcnt]; + } + } +} + +static void +h8300h_timer8(cpu_state_type *cpu,int cycles) +{ + static unsigned char tcsr[4]={0x00,0x00,0x00,0x00}; + const int base[4]={0xffff80,0xffff81,0xffff90,0xffff91}; + static unsigned int prev_cycle=0; + int cyc; + cyc=(unsigned int)cycles-prev_cycle; + prev_cycle=cycles; + timer8sub(base,tcsr,cyc,cpu,4); +} + +static void +h8300s_timer8(cpu_state_type *cpu,int cycles) +{ + static unsigned char tcsr[2]={0x00,0x00}; + const int base[2]={0xffffb0,0xffffb1}; + static unsigned int prev_cycle=0; + int cyc; + cyc=(unsigned int)cycles-prev_cycle; + prev_cycle=cycles; + timer8sub(base,tcsr,cyc,cpu,2); +} + +static unsigned int complete_time(cpu_state_type *cpu,int cycles) +{ + int length; + int div[]={1,4,16,64}; + length=(SMR & 0x40)?7:8; + length+=(SMR & 0x20)?1:0; + length+=(SMR & 0x08)?1:0; + length+=2; + return length*32*div[SMR & 0x03]*BRR+cycles; +} + +static void send_data(int txd) +{ + char dt; + dt=txd; + write(scifd,&dt,1); + fsync(scifd); +} + +static int rcv_data(int *rxd) +{ + char rd; + if(read(scifd,&rd,1)>0) { + *rxd=rd; + return 1; + } else + return 0; +} + +static int sci(cpu_state_type *cpu,int cycles) +{ + static int tx_end_time=0; + static int rx_end_time=0; + static int data=-1; + ssr &= SSR; + if((SCR & 0x20) && !(ssr & 0x80)) { + send_data(TDR); + ssr |= 0x80; + tx_end_time=complete_time(cpu,cycles); + } + if ((data == -1) && !rcv_data(&data)) + data = -1; + if((data != -1) && (SCR & 0x10) && ((rx_end_time==0) || (rx_end_time-cycles)<0)) { + if(ssr & 0x40) { + ssr |= 0x20; + } else { + RDR=data; + ssr |= 0x40; + data=-1; + } + rx_end_time=complete_time(cpu,cycles); + } + if((tx_end_time>0) && (tx_end_time-cycles)<0) { + if(ssr & 0x80) { + ssr |= 0x04; + } + } + SSR = ssr; +} + +static int +h8300h_intcont(cpu_state_type *cpu) +{ + struct INT_LIST { + int vector; + int isr_adr; + unsigned char isr_mask; + int ier_adr; + unsigned char ier_mask; + } int_table[]= { + {36,0xffff82,0x40,0xffff80,0x40}, + {37,0xffff82,0x80,0xffff80,0x80}, + {38,0xffff83,0x40,0xffff81,0x40}, + {38,0xffff83,0x80,0xffff81,0x40}, + {39,0xffff82,0x20,0xffff80,0x20}, + {39,0xffff83,0x20,0xffff81,0x20}, + {40,0xffff92,0x40,0xffff90,0x40}, + {41,0xffff92,0x80,0xffff90,0x80}, + {42,0xffff93,0x40,0xffff91,0x40}, + {42,0xffff93,0x80,0xffff91,0x40}, + {43,0xffff92,0x20,0xffff90,0x20}, + {43,0xffff93,0x20,0xffff91,0x20}, + {52,0xffffb4,0x38,0xffffb2,0x40}, + {53,0xffffb4,0x40,0xffffb2,0x40}, + {54,0xffffb4,0x80,0xffffb2,0x80}, + {55,0xffffb4,0x04,0xffffb2,0x04} + }; + int irqno; + for (irqno=0;irqnomemory[int_table[irqno].ier_adr]&int_table[irqno].ier_mask) + if(cpu->memory[int_table[irqno].isr_adr]&int_table[irqno].isr_mask) + return int_table[irqno].vector; + } + return 0; +} + +static int +h8300s_intcont(cpu_state_type *cpu) +{ + struct INT_LIST { + int vector; + int isr_adr; + unsigned char isr_mask; + int ier_adr; + unsigned char ier_mask; + } int_table[]= { + {72,0xffffb2,0x40,0xffffb0,0x40}, + {73,0xffffb2,0x80,0xffffb0,0x80}, + {76,0xffffb3,0x40,0xffffb1,0x40}, + {77,0xffffb3,0x80,0xffffb1,0x40}, + {74,0xffffb2,0x20,0xffffb0,0x20}, + {78,0xffffb3,0x20,0xffffb1,0x20}, + {88,0xffff7c,0x38,0xffff7a,0x40}, + {89,0xffff7c,0x40,0xffff7a,0x40}, + {90,0xffff7c,0x80,0xffff7a,0x80}, + {91,0xffff7c,0x04,0xffff7a,0x04} + }; + int irqno; + for (irqno=0;irqnomemory[int_table[irqno].ier_adr]&int_table[irqno].ier_mask) + if(cpu->memory[int_table[irqno].isr_adr]&int_table[irqno].isr_mask) + return int_table[irqno].vector; + } + return 0; +} + +int +iosimulation(cpu_state_type *cpu,int cycles) +{ + if (h8300hmode && !h8300smode) h8300h_timer8(cpu,cycles); + if (h8300smode) h8300s_timer8(cpu,cycles); + sci(cpu,cycles); + if (h8300hmode && !h8300smode) return h8300h_intcont(cpu); + if (h8300smode) return h8300s_intcont(cpu); +} + +void init_ioregs(cpu_state_type *cpu) +{ + struct INITTABLE { + int addr; + short data; + }; + const struct INITTABLE h8300h_reg_ini[] = { + 0xffff80,0x00, + 0xffff81,0x00, + 0xffff82,0x00, + 0xffff83,0x00, + 0xffff84,0xff, + 0xffff85,0xff, + 0xffff86,0xff, + 0xffff87,0xff, + 0xffff88,0x00, + 0xffff89,0x00, + 0xffff90,0x00, + 0xffff91,0x00, + 0xffff92,0x00, + 0xffff93,0x00, + 0xffff94,0xff, + 0xffff95,0xff, + 0xffff96,0xff, + 0xffff97,0xff, + 0xffff98,0x00, + 0xffff99,0x00, + 0xffffb0,0x00, + 0xffffb1,0xff, + 0xffffb2,0x00, + 0xffffb3,0xff, + 0xffffb4,0x84, + 0xffffb8,0x00, + 0xffffb9,0xff, + 0xffffba,0x00, + 0xffffbb,0xff, + 0xffffbc,0x84, + 0xffffc0,0x00, + 0xffffc1,0xff, + 0xffffc2,0x00, + 0xffffc3,0xff, + 0xffffc4,0x84, + }; + const struct INITTABLE h8300s_reg_ini[] = { + 0xffffb0,0x00, + 0xffffb1,0x00, + 0xffffb2,0x00, + 0xffffb3,0x00, + 0xffffb4,0xff, + 0xffffb5,0xff, + 0xffffb6,0xff, + 0xffffb7,0xff, + 0xffffb8,0x00, + 0xffffb9,0x00, + 0xffff78,0x00, + 0xffff79,0xff, + 0xffff7a,0x00, + 0xffff7b,0xff, + 0xffff7c,0x84, + 0xffff80,0x00, + 0xffff81,0xff, + 0xffff82,0x00, + 0xffff83,0xff, + 0xffff84,0x84, + 0xffff88,0x00, + 0xffff89,0xff, + 0xffff8a,0x00, + 0xffff8b,0xff, + 0xffff8c,0x84, + }; + int c; + if (h8300hmode && !h8300smode) { + sci_base=0xffffb0; + for(c=0;cmemory[h8300h_reg_ini[c].addr]=h8300h_reg_ini[c].data; + } + if (h8300smode) { + sci_base=0xffff78; + for(c=0;cmemory[h8300s_reg_ini[c].addr]=h8300s_reg_ini[c].data; + } + ssr = 0x84; +} + +char *openpty(void) +{ + const char nm[]="0123456789ABCDEF"; + static char ptyname[16]; + int c1,c2,fd; + struct termios attr; + fd = open("/dev/ptmx",O_RDWR|O_NONBLOCK); + if(fd >= 0) { + grantpt(fd); + unlockpt(fd); + strncpy(ptyname,ptsname(fd),sizeof(ptyname)-1); + ptyname[sizeof(ptyname)-1]='\0'; + } else { + for(c1='a';c1<='z';c1++) + for(c2=0;c2= 0) { + scifd=fd; + tcgetattr(scifd,&attr); + memcpy(&old_attr,&attr,sizeof(struct termios)); + attr.c_lflag&=~ICANON; + attr.c_cc[VMIN]=0; + attr.c_cc[VTIME]=0; + tcsetattr(scifd,TCSAFLUSH,&attr); + return ptyname; + } else + return NULL; +} + +void closepty(void) +{ + struct termios attr; + if(scifd!=-1) { + tcsetattr(scifd,TCSAFLUSH,&old_attr); + close(scifd); + } +}