Ð þí) 8&L(¿&xlnx,zynq-cc108xlnx,zynq-7000&Xilinx CC108 boardcpuscpu@0arm,cortex-a9,cpu8<CèQ] ,+B@B@ncpu@1arm,cortex-a9,cpu8<nfpga-full fpga-regionvpmu@f8891000arm,cortex-a9-pmu†‘8ø‰ø‰0fixedregulatorregulator-fixed¢VCCPINT±B@ÉB@áónreplicator arm,coresight-static-replicator<./apb_pclkdbg_trcdbg_apbout-portsport@08endpointn port@18endpointn in-portsportendpointnaxi simple-bus‘adc@f8007100xlnx,zynq-xadc-1.00.a8øq  †‘< can@e0008000xlnx,zynq-can-1.0 #disabled<$ can_clkpclk8à€ †‘*@8@can@e0009000xlnx,zynq-can-1.0 #disabled<% can_clkpclk8à †3‘*@8@gpio@e000a000xlnx,zynq-gpio-1.0F<*Rbw‘ †8à i2c@e0004000cdns,i2c-r1p10 #disabled<&‘ †8à@i2c@e0005000cdns,i2c-r1p10 #disabled<'‘ †08àPinterrupt-controller@f8f01000arm,cortex-a9-gicwb8øðøðncache-controller@f8f02000arm,pl310-cache8øð  † ˆ ™©·memory-controller@f8006000xlnx,zynq-ddrc-a058ø`serial@e0000000xlnx,xuartpscdns,uart-r1p8#okay<(uart_clkpclk8à †serial@e0001000xlnx,xuartpscdns,uart-r1p8 #disabled<)uart_clkpclk8à †2spi@e0006000xlnx,zynq-spi-r1p68à` #disabled‘ †<" ref_clkpclkspi@e0007000xlnx,zynq-spi-r1p68àp #disabled‘ †1<# ref_clkpclkethernet@e000b000cdns,zynq-gemcdns,gem8à°#okay †< pclkhclktx_clk Ãrgmii-idÌethernet-phy@18 ,ethernet-phynethernet@e000c000cdns,zynq-gemcdns,gem8àÀ #disabled †-<pclkhclktx_clkmemory-controller@e000e000!arm,pl353-smc-r2p1arm,primecell8àà #disabledmemclkapb_pclk< ,0áâänand-controller@0,0arm,pl353-nand-r2p1 8 #disabledmmc@e0100000arasan,sdhci-8.9a #disabledclk_xinclk_ahb< ‘ †8àmmc@e0101000arasan,sdhci-8.9a#okayclk_xinclk_ahb<!‘ †/8à×áslcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8øn clkc@100íxlnx,ps7-clkcújarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8nrstc@200xlnx,zynq-reset8H& pinctrl@700xlnx,pinctrl-zynq8& dmac@f8003000arm,pl330arm,primecell8ø0‘.-abortdma0dma1dma2dma3dma4dma5dma6dma7l† ()*+=HV< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08øp‘ †< ref_clk& ntimer@f8f00200arm,cortex-a9-global-timer8øð  † ‘<timer@f8001000‘$†    cdns,ttc<8øtimer@f8002000‘$†%&' cdns,ttc<8ø timer@f8f00600‘ † arm,cortex-a9-twd-timer8øð <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2#okay<‘ †8à dulpimhostu usb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2#okay<‘ †,8à0dulpimhostu watchdog@f8005000<-cdns,wdt-r1p2‘ † 8øP} etb@f8801000"arm,coresight-etb10arm,primecell8ø€<./apb_pclkdbg_trcdbg_apbin-portsportendpoint ntpiu@f8803000!arm,coresight-tpiuarm,primecell8ø€0<./apb_pclkdbg_trcdbg_apbin-portsportendpoint nfunnel@f8804000*arm,coresight-static-funnelarm,primecell8ø€@<./apb_pclkdbg_trcdbg_apbout-portsportendpointnin-portsport@08endpointnport@18endpointnport@28endpointptm@f889c000"arm,coresight-etm3xarm,primecell8ø‰À<./apb_pclkdbg_trcdbg_apb‰out-portsportendpointnptm@f889d000"arm,coresight-etm3xarm,primecell8ø‰Ð<./apb_pclkdbg_trcdbg_apb‰out-portsportendpointnaliases/axi/ethernet@e000b000—/axi/serial@e0000000chosenŸ¨serial0:115200n8memory@0,memory8 phy0usb-nop-xceiv´n phy1usb-nop-xceiv´n  #address-cells#size-cellscompatiblemodeldevice_typeregclocksclock-latencycpu0-supplyoperating-pointsphandlefpga-mgrrangesinterruptsinterrupt-parentregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-onclock-namesremote-endpointstatustx-fifo-depthrx-fifo-depth#gpio-cellsgpio-controllerinterrupt-controller#interrupt-cellsarm,data-latencyarm,tag-latencycache-unifiedcache-levelphy-modephy-handlebroken-cdwp-inverted#clock-cellsfclk-enableclock-output-names#reset-cellssysconinterrupt-names#dma-cells#dma-channels#dma-requestsphy_typedr_modeusb-phytimeout-seccpuethernet0serial0bootargsstdout-path#phy-cells