_+8Z(7Z,Merrii A80 Optimus Board'2merrii,a80-optimusallwinner,sun9i-a80aliases=/soc@20000/ethernet@830000G/soc@20000/serial@7000000O/soc@20000/serial@7001000cpuscpu@02arm,cortex-a7Wcpuctallwinner,sun9i-a80-smpcpu@12arm,cortex-a7Wcpuctallwinner,sun9i-a80-smpcpu@22arm,cortex-a7Wcpuctallwinner,sun9i-a80-smpcpu@32arm,cortex-a7Wcpuctallwinner,sun9i-a80-smpcpu@1002arm,cortex-a15Wcpuctallwinner,sun9i-a80-smpcpu@1012arm,cortex-a15Wcpuctallwinner,sun9i-a80-smpcpu@1022arm,cortex-a15Wcpuctallwinner,sun9i-a80-smpcpu@1032arm,cortex-a15Wcpuctallwinner,sun9i-a80-smptimer2arm,armv7-timer0   tn6clocks clk-24M 2fixed-clocktn6osc24Mclk-32k2fixed-factor-clockosc32k mii_phy_tx_clk 2fixed-clockt}x@ mii_phy_txgmac_int_tx_clk 2fixed-clocktsY@ gmac_int_txclk@8000302allwinner,sun7i-a20-gmac-clk0 gmac_txclk@80014102allwinner,sun9i-a80-cpus-clk   cpus clk-ahbs2fixed-factor-clock ahbs clk@800141c2allwinner,sun8i-a23-apb0-clk apbs clk@8001428#2allwinner,sun9i-a80-apbs-gates-clk( 8 apbs_pioapbs_irapbs_timerapbs_rsbapbs_uartapbs_1wireapbs_i2c0apbs_i2c1apbs_ps2_0apbs_ps2_1apbs_dmaapbs_i2s0apbs_i2s1apbs_twd>clk@8001450P2allwinner,sun4i-a10-mod0-clk r_1wireclk@8001454T2allwinner,sun4i-a10-mod0-clk r_ir?display-engine#2allwinner,sun9i-a80-display-engine  2disabledsoc@20000 2simple-bus sram@20000 2mmio-sram smp-sram@10002allwinner,sun9i-a80-smp-sramethernet@8300002allwinner,sun7i-a20-gmacT R9macirq  aIstmmacethallwinner_gmac_txU  \stmmacethhq2okaydefault rgmii-idmdio2snps,dwmac-mdioethernet-phy@1usb@a00000&2allwinner,sun9i-a80-ehcigeneric-ehci H Uusb2okayusb@a00400&2allwinner,sun9i-a80-ohcigeneric-ohci I Uusb2okayphy@a008002allwinner,sun9i-a80-usb-phy IphyU\phy2okayusb@a01000&2allwinner,sun9i-a80-ehcigeneric-ehci J Uusb 2disabledphy@a018002allwinner,sun9i-a80-usb-phy  Iphyhsic_12Mhsic_480MU \phyhsic 2disabledhsicusb@a02000&2allwinner,sun9i-a80-ehcigeneric-ehci  L Uusb2okayusb@a02400&2allwinner,sun9i-a80-ohcigeneric-ohci$ M Uusb2okayphy@a028002allwinner,sun9i-a80-usb-phy(   Iphyhsic_12Mhsic_480MU \phyhsic2okayclock@a080002allwinner,sun9i-a80-usb-clks  ` Ibushosccpucfg@17000002allwinner,sun9i-a80-cpucfgpcrypto@1c020002allwinner,sun9i-a80-crypto  PU  S .Ibusmodmmc@1c0f0002allwinner,sun9i-a80-mmc   ! # "IahbmmcoutputsampleU\ahb <2okaydefault mmc@1c100002allwinner,sun9i-a80-mmc   $ & %IahbmmcoutputsampleU\ahb =2okaydefault ,! 7mmc@1c110002allwinner,sun9i-a80-mmc   ' ) (IahbmmcoutputsampleU\ahb >2okaydefault" 7Emmc@1c120002allwinner,sun9i-a80-mmc    * , +IahbmmcoutputsampleU\ahb ? 2disabledclk@1c13000#2allwinner,sun9i-a80-mmc-config-clk0 TU 0mmc0_configmmc1_configmmc2_configmmc3_configinterrupt-controller@1c41000 2arm,gic-400  @ ` Vk  cci@1c90000 2arm,cci-400 slave-if@40002arm,cci-400-ctrl-if|ace@slave-if@50002arm,cci-400-ctrl-if|acePpmu@90002arm,cci-400-pmu,r1P<clock@30000002allwinner,sun9i-a80-de-clks0 7 6 k ImoddrambusU #display-frontend@3100000%2allwinner,sun9i-a80-display-frontend ] ###  IahbmodramU# portsport@1endpoint$,display-frontend@3140000%2allwinner,sun9i-a80-display-frontend ^ ###  IahbmodramU#portsport@1endpoint%/display-backend@3200000$2allwinner,sun9i-a80-display-backend  _ ### IahbmodramU#portsport@0endpoint@0&-endpoint@1'0port@1endpoint(2display-backend@3240000$2allwinner,sun9i-a80-display-backend$ ` ### IahbmodramU#portsport@0endpoint@0).endpoint@1*1port@1endpoint+4deu@33000002allwinner,sun9i-a80-deu0 \ ### IahbmodramU#portsport@0endpoint,$port@1endpoint@0-&endpoint@1.)deu@33400002allwinner,sun9i-a80-deu4 \ ### IahbmodramU#portsport@0endpoint/%port@1endpoint@00'endpoint@11*drc@34000002allwinner,sun9i-a80-drc@ [ ### IahbmodramU#portsport@0endpoint2(port@1endpoint36drc@34400002allwinner,sun9i-a80-drcD [ ## # IahbmodramU# portsport@0endpoint4+port@1endpoint57lcd-controller@3c000002allwinner,sun9i-a80-tcon-lcd V f : Iahbtcon-ch0U    \lcdedplvdstcon0-pixel-clockportsport@0endpoint63port@1lcd-controller@3c100002allwinner,sun9i-a80-tcon-tv W g ; Iahbtcon-ch1U  \lcdedpportsport@0endpoint75port@1clock@60000002allwinner,sun9i-a80-ccu  Ihosclosc timer@6000c002allwinner,sun4i-a10-timer H watchdog@6000ca02allwinner,sun6i-a31-wdt   pinctrl@60008002allwinner,sun9i-a80-pinctrl< x oIapbhoscloscVk89: ;gmac-rgmii-pinsB'PA0PA1PA2PA3PA4PA5PA7PA8PA9PA10PA12PA13PA15PA16PA17,gmac5(i2c3-pins 'PG10PG11,i2c3lcd0-rgb888-pins'PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27,lcd0mmc0-pins'PF0PF1PF2PF3PF4PF5,mmc05Dmmc1-pins'PG0PG1PG2PG3PG4PG5,mmc15Dmmc2-8bit-pins3'PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC16,mmc25(D"uart0-ph-pins 'PH12PH13,uart0<uart4-pins'PG12PG13PG14PG15,uart4serial@70000002snps,dw-apb-uart Q[ |U -2okaydefault<serial@70004002snps,dw-apb-uart Q[ }U . 2disabledserial@70008002snps,dw-apb-uart Q[ ~U / 2disabledserial@7000c002snps,dw-apb-uart  Q[ U 0 2disabledserial@70010002snps,dw-apb-uart Q[ U 1 2disabledserial@70014002snps,dw-apb-uart Q[ U 2 2disabledi2c@70028002allwinner,sun6i-a31-i2c(  wU ( 2disabledi2c@7002c002allwinner,sun6i-a31-i2c,  xU ) 2disabledi2c@70030002allwinner,sun6i-a31-i2c0  yU * 2disabledi2c@70034002allwinner,sun6i-a31-i2c4  zU + 2disabledi2c@70038002allwinner,sun6i-a31-i2c8  {U , 2disabledwatchdog@80010002allwinner,sun6i-a31-wdt  $ prcm@80014002allwinner,sun9i-a80-prcmreset@80014b0 2allwinner,sun6i-a31-clock-reset@interrupt-controller@80015a02allwinner,sun9i-a80-nmiVk  Dir@80020002allwinner,sun6i-a31-ir %default=  >?IapbirU@ @2okayserial@80028002snps,dw-apb-uart( &Q[ >U@ 2disabledpinctrl@8002c002allwinner,sun9i-a80-r-pinctrl,-. >IapbhoscloscU@VkhAvBFr-ir-pins'PL6 ,s_cir_rx=r-rsb-pins'PN0PN1,s_rsb5DCrsb@80034002allwinner,sun8i-a23-rsb4 ' >t-U@defaultC2okaypmic@3a3D2x-powers,axp809Vkregulatorsaldo1-- vcc33-usbhaldo2w@w@vcc-pb-io-cam9aldo3dc5ldo 5vdd-cpus-09-usbhdc1swdcdc1--vcc-3vdcdc2 5vdd-gpudcdc3 5 vdd-cpuadcdc4 5vdd-sys-usb0-hdmidcdc5hX vcc-dramdldo12Z2Z vcc-wifidldo2--vcc-plAeldo1OO vcc-dvdd-cameldo2w@w@vcc-pe:eldo3--vcc-pm-codec-io1Bldo_io0--vcc-pg;ldo_io1&%&%vcc-pa-gmac-2v58rtc_ldovcc-rtc-vdd1v8-ioswpmic@7452x-powers,axp806EDVkEregulatorsaldo1--avccaldo2s_aldo2aldo3s_aldo3bldo1vcc18-efuse-adc-display-csibldo2vdd18-drampll-vcc18-pll-cpvddbldo3bldo4  vcc12-hsiccldo12Z2Z vcc-gmac-phycldo2** afvcc-camcldo3--vcc-io-wifi-codec-io2 dcdca 5 vdd-cpubdcdcd 5vdd-vpudcdce  vcc-bldo-codec-ldoinEsws_swcodec@e892x-powers,ac100codec2x-powers,ac100-codecF 4M_addaGrtc2x-powers,ac100-rtcD Gcko1_rtccko2_rtccko3_rtcchosenserial0:115200n8leds 2gpio-ledsled2 optimus:led2:usrled3 optimus:led3:usrFled4 optimus:led4:usrusb1-vbus2regulator-fixed usb1-vbusLK@LK@&usb3-vbus2regulator-fixed usb3-vbusLK@LK@&wifi-pwrseq2mmc-pwrseq-simple  Iext_clock+F! #address-cells#size-cellsinterrupt-parentmodelcompatibleethernet0serial0serial1device_typecci-control-portclock-frequencyenable-methodreginterruptsarm,cpu-registers-not-fw-configuredranges#clock-cellsclock-output-namesphandleclock-divclock-multclocksclock-indicesallwinner,pipelinesstatusinterrupt-namesclock-namesresetsreset-namessnps,pblsnps,fixed-burstsnps,force_sf_dma_modepinctrl-namespinctrl-0phy-handlephy-modephy-supplyphysphy-names#phy-cellsphy_type#reset-cellsvmmc-supplybus-widthcd-gpiosvqmmc-supplymmc-pwrseqnon-removablecap-mmc-hw-resetinterrupt-controller#interrupt-cellsinterface-typeremote-endpointgpio-controller#gpio-cellsvcc-pa-supplyvcc-pb-supplyvcc-pc-supplyvcc-pd-supplyvcc-pe-supplyvcc-pf-supplyvcc-pg-supplyvcc-ph-supplypinsfunctiondrive-strengthbias-pull-upreg-shiftreg-io-widthvcc-pl-supplyvcc-pm-supplyregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-namebldoin-supplyregulator-enable-ramp-delaystdout-pathlabelenable-active-highgpioreset-gpios