Y8V(U ,CSQ CS908 top set box2csq,cs908allwinner,sun6i-a31saliases=/soc/ethernet@1c30000G/soc/serial@1c28000chosen OVserial0:115200n8framebuffer-lcd0-hdmi02allwinner,simple-framebuffersimple-framebufferbde_be0-lcd0-hdmi@u3/2wz |disabledframebuffer-lcd002allwinner,simple-framebuffersimple-framebuffer bde_be0-lcd00u3/wz |disabledtimer2arm,armv7-timer0   n6cpusallwinner,sun6i-a31 cpu@02arm,cortex-a7cpuu aO /O SB@cpu@12arm,cortex-a7cpuu aO /O SB@cpu@22arm,cortex-a7cpuu aO /O SB@cpu@32arm,cortex-a7cpuu aO /O SB@thermal-zonescpu-thermal,:cooling-mapsmap0J0Otripscpu_alert0^pjpassivecpu_crit^j criticalpmu2arm,cortex-a7-pmu0xyz{clocks Oclk-24Mu 2fixed-clockn6Posc24Mclk-32ku 2fixed-clockP ext_osc32k3clk-mii-phy-txu 2fixed-clock}x@ mii_phy_tx clk-gmac-int-txu 2fixed-clocksY@ gmac_int_tx clk@1c200d0u2allwinner,sun7i-a20-gmac-clku gmac_tx display-engine$2allwinner,sun6i-a31s-display-engine  |disabledsoc 2simple-bus Odma-controller@1c020002allwinner,sun6i-a31-dma  2u lcd-controller@1c0c0002allwinner,sun6i-a31s-tcon V ) lcdlvds u/ahbtcon-ch0tcon-ch1lvds-alttcon0-pixel-clockuports port@0 endpoint@01endpoint@1+port@1 endpoint@1lcd-controller@1c0d0002allwinner,sun6i-a31-tcon W ) lcdlvds u0ahbtcon-ch0tcon-ch1lvds-alttcon1-pixel-clockuports port@0 endpoint@02endpoint@1,port@1 endpoint@1mmc@1c0f0002allwinner,sun7i-a20-mmc uOQPahbmmcoutputsampleahb <default |disabled mmc@1c100002allwinner,sun7i-a20-mmc uRTSahbmmcoutputsampleahb =default |disabled mmc@1c110002allwinner,sun7i-a20-mmc uUWVahbmmcoutputsampleahb > |disabled mmc@1c120002allwinner,sun7i-a20-mmc  uXZYahbmmcoutputsample ahb ? |disabled hdmi@1c160002allwinner,sun6i-a31-hdmi` X(u2 ahbmodddcpll-0pll-1&ddc-txddc-rxaudio-tx  |disabledports port@0 endpoint@0endpoint@1port@1usb@1c190002allwinner,sun6i-a31-musbu( G0mc@EusbOVhost|okayphy@1c194002allwinner,sun6i-a31-usb-phy^phy_ctrlpmu1pmu2udefusb0_phyusb1_phyusb2_phy!usb0_resetusb1_resetusb2_reset|okayhusb@1c1a000&2allwinner,sun6i-a31-ehcigeneric-ehci Hu)@Eusb|okayusb@1c1a400&2allwinner,sun6i-a31-ohcigeneric-ohci Iu+g@Eusb |disabledusb@1c1b000&2allwinner,sun6i-a31-ehcigeneric-ehci Ju*@Eusb|okayusb@1c1b400&2allwinner,sun6i-a31-ohcigeneric-ohci Ku,h@Eusb|okayusb@1c1c400&2allwinner,sun6i-a31-ohcigeneric-ohci Mu-i |disabledclock@1c200002allwinner,sun6i-a31-ccu u hoscloscuspinctrl@1c208002allwinner,sun6i-a31s-pinctrl0 u@apbhoscloscgmac-gmii-pinsPA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15PA16PA17PA18PA19PA20PA21PA22PA23PA24PA25PA26PA27gmacgmac-mii-pinsTPA0PA1PA2PA3PA8PA9PA11PA12PA13PA14PA19PA20PA21PA22PA23PA24PA26PA27gmac!gmac-rgmii-pinsFPA0PA1PA2PA3PA9PA10PA11PA12PA13PA14PA19PA20PA25PA26PA27gmac(i2c0-pins PH14PH15i2c0i2c1-pins PH16PH17i2c1i2c2-pins PH18PH19i2c2lcd0-rgb888-pinsPD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27lcd0mmc0-pinsPF0PF1PF2PF3PF4PF5mmc0mmc1-pinsPG0PG1PG2PG3PG4PG5mmc1mmc2-4bit-pinsPC6PC7PC8PC9PC10PC11mmc2mmc2-8bit-emmc-pins3PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc2mmc3-8bit-emmc-pins3PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC24mmc3(spdif-tx-pinPH28spdifuart0-ph-pins PH20PH21uart0timer@1c20c002allwinner,sun4i-a10-timer Huwatchdog@1c20ca02allwinner,sun6i-a31-wdt  uspdif@1c210002allwinner,sun6i-a31-spdif u>c+ apbspdif  &rxtx |disabledi2s@1c220002allwinner,sun6i-a31-i2s  uAa-apbmod  &rxtx |disabledi2s@1c224002allwinner,sun6i-a31-i2s$ uBb.apbmod  &rxtx |disabledlradc@1c228002allwinner,sun4i-a10-lradc-keys(  |disabledrtp@1c250002allwinner,sun6i-a31-tsP serial@1c280002snps,dw-apb-uart€ uG3  &rxtx|okaydefaultserial@1c284002snps,dw-apb-uart„ uH4  &rxtx |disabledserial@1c288002snps,dw-apb-uartˆ uI5  &rxtx |disabledserial@1c28c002snps,dw-apb-uartŒ uJ6 &rxtx |disabledserial@1c290002snps,dw-apb-uart uK7 &rxtx |disabledserial@1c294002snps,dw-apb-uart” uL8  &rxtx |disabledi2c@1c2ac002allwinner,sun6i-a31-i2c¬ uC/default |disabled i2c@1c2b0002allwinner,sun6i-a31-i2c° uD0default |disabled i2c@1c2b4002allwinner,sun6i-a31-i2c´ uE1default |disabled i2c@1c2b8002allwinner,sun6i-a31-i2c¸ uF2 |disabled ethernet@1c300002allwinner,sun7i-a20-gmacT R0macirq u! stmmacethallwinner_gmac_tx  stmmaceth*3D|okaydefault!["fmiimdio2snps,dwmac-mdio ethernet-phy@1"crypto-engine@1c1500062allwinner,sun6i-a31-cryptoallwinner,sun4i-a10-cryptoP Pu\ahbmodahbcodec@1c22c002allwinner,sun6i-a31-codec, u= apbcodec*  &rxtx |disabledtimer@1c6000082allwinner,sun6i-a31-hstimerallwinner,sun7i-a20-hstimer03456u#spi@1c680002allwinner,sun6i-a31-spiƀ Au$]ahbmod  &rxtx |disabled spi@1c690002allwinner,sun6i-a31-spiƐ Bu%^ahbmod  &rxtx |disabled spi@1c6a0002allwinner,sun6i-a31-spiƠ Cu&_ahbmod  &rxtx |disabled spi@1c6b0002allwinner,sun6i-a31-spiư Du'`ahbmod  &rxtx |disabled interrupt-controller@1c81000 2arm,gic-400  @ `   display-frontend@1e00000%2allwinner,sun6i-a31-display-frontend ]u5|u ahbmodram! ports port@1 endpoint@0#-endpoint@1$'display-frontend@1e20000%2allwinner,sun6i-a31-display-frontend ^u6}v ahbmodram" ports port@1 endpoint@0%.endpoint@1&(display-backend@1e40000$2allwinner,sun6i-a31-display-backend `u4{x ahbmodram ports port@0 endpoint@0'$endpoint@1(&port@1 endpoint@1)*drc@1e500002allwinner,sun6i-a31-drc [u<r ahbmodram(ports port@0 endpoint@1*)port@1 endpoint@0+endpoint@1,display-backend@1e60000$2allwinner,sun6i-a31-display-backend _u3zw ahbmodramports port@0 endpoint@0-#endpoint@1.%port@1endpoint/0drc@1e700002allwinner,sun6i-a31-drc [u;q ahbmodram'ports port@0endpoint0/port@1 endpoint@01endpoint@12rtc@1f00000u2allwinner,sun6i-a31-rtcT()u3osc32kinterrupt-controller@1f00c002allwinner,sun6i-a31-r-intc  prcm@1f014002allwinner,sun6i-a31-prcmar100_clk2allwinner,sun6i-a31-ar100-clkuu  ar1004ahb0_clk2fixed-factor-clockuoyu4ahb05apb0_clk2allwinner,sun6i-a31-apb0-clkuu5apb06apb0_gates_clk#2allwinner,sun6i-a31-apb0-gates-clkuu6Dapb0_pioapb0_irapb0_timerapb0_p2wiapb0_uartapb0_1wireapb0_i2c7ir_clku2allwinner,sun4i-a10-mod0-clk uir8apb0_rst 2allwinner,sun6i-a31-clock-resets9cpucfg@1f01c002allwinner,sun6i-a31-cpuconfigir@1f020002allwinner,sun6i-a31-ir u78apbir9 % @|okaydefault:pinctrl@1f02c002allwinner,sun6i-a31-r-pinctrl,-.u7apbhosclosc9s-ir-rx-pinPL4s_ir:s-p2wi-pinsPL0PL1s_p2wi;i2c@1f034002allwinner,sun6i-a31-p2wi4 'u79default; |disabled  interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0serial0rangesstdout-pathallwinner,pipelineclocksstatusinterruptsclock-frequencyarm,cpu-registers-not-fw-configuredenable-methoddevice_typeregclock-latencyoperating-points#cooling-cellsphandlepolling-delay-passivepolling-delaythermal-sensorstripcooling-devicetemperaturehysteresis#clock-cellsclock-accuracyclock-output-namesallwinner,pipelinesresets#dma-cellsdmasreset-namesclock-namesremote-endpointallwinner,tcon-channelpinctrl-namespinctrl-0dma-namesinterrupt-namesphysphy-namesextcondr_modereg-names#phy-cells#reset-cellsgpio-controllerinterrupt-controller#interrupt-cells#gpio-cellspinsfunctiondrive-strengthbias-pull-up#sound-dai-cells#thermal-sensor-cellsreg-shiftreg-io-widthsnps,pblsnps,fixed-burstsnps,force_sf_dma_modephy-handlephy-modeclock-divclock-mult