8p( '8radxa,rockpi-erockchip,rk3328 +7Radxa ROCK Pi Ealiases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci  cpu@1cpuarm,cortex-a53xpsci  cpu@2cpuarm,cortex-a53xpsci  cpu@3cpuarm,cortex-a53xpsci  idle-statespscicpu-sleeparm,idle-state*;Rxcsl2-cache0cacheopp_table0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardi2sHDMI  disabledsimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mCi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7pi2s_clki2s_hclk|  txrx  disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8pi2s_clki2s_hclk|txrx okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9pi2s_clki2s_hclk|txrx  disabledspdif@ff030000rockchip,rk3328-spdif .: pmclkhclk| txdefault  disabledpdm@ff040000 rockchip,pdm=Rppdm_clkpdm_hclk|rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd8io-domains"rockchip,rk3328-io-voltage-domain okaygpiorockchip,rk3328-grf-gpio/power-controller!rockchip,rk3328-power-controller;+;power-domain@6;power-domain@5;power-domain@8F;reboot-modesyscon-reboot-modeOVRBbRBpRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&pbaudclkapb_pclk|txrxdefault    disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'pbaudclkapb_pclk|txrxdefault !"#  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(pbaudclkapb_pclk|txrxdefault$ okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 pi2cpclkdefault%  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 pi2cpclkdefault& okaypmic@18rockchip,rk805 '@]xin32krk805-clkout2/default()))))regulatorsDCDC_REG1vdd_log)=O 4g 0regulator-state-memB@DCDC_REG2vdd_arm)=O 4g 0regulator-state-mem~DCDC_REG3vcc_ddr)=regulator-state-memDCDC_REG4vcc_io)=O2Zg2Zregulator-state-mem2ZLDO_REG1vcc_18)=Ow@gw@9regulator-state-memw@LDO_REG2 vcc18_emmc)=Ow@gw@regulator-state-memw@LDO_REG3vdd_10)=OB@gB@regulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 pi2cpclkdefault*  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: pi2cpclkdefault+  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ pspiclkapb_pclk| txrxdefault,-./  disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< ppwmpclkdefault0  disabledpwm@ff1b0010rockchip,rk3328-pwm< ppwmpclkdefault1  disabledpwm@ff1b0020rockchip,rk3328-pwm < ppwmpclkdefault2  disabledpwm@ff1b0030rockchip,rk3328-pwm0 2< ppwmpclkdefault3  disableddma-controller@ff1f0000arm,pl330arm,primecell@ papb_pclkthermal-zonessoc-thermal +4tripstrip-point0;pGpassivetrip-point1;LGpassive5soc-crit;sG criticalcooling-mapsmap0R50W ftsadc@ff250000rockchip,rk3328-tsadc% :s$P$ptsadcapb_pclkinitdefaultsleep676B tsadc-apb8 okay4efuse@ff260000rockchip,rk3328-efuse&P+> ppclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aDadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( P%psaradcapb_pclkV saradc-apb okay9dgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"&gpgpmmupppp0ppmmu0pp1ppmmu1 pbuscorefiommu@ff330200rockchip,iommu3 ` &h265e_mmu paclkiface6  disablediommu@ff340800rockchip,iommu4@ b &vepu_mmuF paclkiface6  disabledvideo-codec@ff350000rockchip,rk3328-vpu5  &vdpuF paclkhclkC:J;iommu@ff350800rockchip,iommu5@  &vpu_mmuF paclkiface6J;:iommu@ff360480rockchip,iommu 6@6@ J &rkvdec_mmuB paclkiface6  disabledvop@ff370000rockchip,rk3328-vop7>  x;paclk_vopdclk_vophclk_vop axiahbdclkC<  disabledport+ endpoint@0X=Biommu@ff373f00rockchip,iommu7?  &vop_mmu; paclkiface6  disabled<hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFpiahbisfrcech>mhdmidefault ?@A8  disabledportsportendpointXB=codec@ff410000rockchip,rk3328-codecA* ppclkmclk8 okayphy@ff430000rockchip,rk3328-hdmi-phyC SCypsysclkrefoclkrefpclk ]hdmi_phy@wD cpu-version  disabled>clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD8@sx=&'(ABDC"\5H4$zCCC|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyCpphyclk ]usb480m_phy@s{E okayEotg-port$;<=&otg-bvalidotg-idlinestate  disabledWhost-port > &linestate okayXmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNpbiuciuciu-driveciu-sampleр okaydefaultFGHIJmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KOpbiuciuciu-driveciu-sampleр  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPpbiuciuciu-driveciu-sampleр okay -<default KLMJethernet@ff540000rockchip,rk3328-gmacT &macirq8dWXZYMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth8W okaysdfNNbinputoOzrgmiidefaultP&mdiosnps,dwmac-mdio+ethernet-phy@1QRdefault S'P SOethernet@ff550000rockchip,rk3328-gmacU8 &macirq8TSSUVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethzrmiioTWboutput okaymdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultUVTusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Mpotgotg@ hW musb2-phy  disabledusb@ff5c0000 generic-ehci\  NEhXmusb okayusb@ff5d0000 generic-ohci]  NEhXmusb  disabledusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`apref_clksuspend_clkbus_clkhost ,utmi_wide5Vn okayinterrupt-controller@ff811000 arm,gic-400@ @ `   pinctrlrockchip,rk3328-pinctrl8+ gpio0@ff210000rockchip,gpio-bank! 3/ggpio1@ff220000rockchip,gpio-bank" 4/Sgpio2@ff230000rockchip,gpio-bank# 5/'gpio3@ff240000rockchip,gpio-bank$ 6/fpcfg-pull-up [pcfg-pull-down cpcfg-pull-none ,Ypcfg-pull-none-2ma , 9bpcfg-pull-up-2ma  9pcfg-pull-up-4ma  9\pcfg-pull-none-4ma , 9_pcfg-pull-down-4ma  9pcfg-pull-none-8ma , 9]pcfg-pull-up-8ma  9^pcfg-pull-none-12ma , 9 `pcfg-pull-up-12ma  9 apcfg-output-high Hpcfg-output-low Tpcfg-input-high  _Zpcfg-input _i2c0i2c0-xfer lYY%i2c1i2c1-xfer lYY&i2c2i2c2-xfer l YY*i2c3i2c3-xfer lYY+i2c3-pins lYYhdmi_i2chdmii2c-xfer lYY@pdm-0pdmm0-clk lYpdmm0-fsync lYpdmm0-sdi0 lYpdmm0-sdi1 lYpdmm0-sdi2 lYpdmm0-sdi3 lYpdmm0-clk-sleep lZpdmm0-sdi0-sleep lZpdmm0-sdi1-sleep lZpdmm0-sdi2-sleep lZpdmm0-sdi3-sleep lZpdmm0-fsync-sleep lZtsadcotp-pin l Y6otp-out l Y7uart0uart0-xfer l Y[uart0-cts l Yuart0-rts l Y uart0-rts-pin l Yuart1uart1-xfer lY[!uart1-cts lY"uart1-rts lY#uart1-rts-pin lYuart2-0uart2m0-xfer lY[uart2-1uart2m1-xfer lY[$spi0-0spi0m0-clk l[spi0m0-cs0 l [spi0m0-tx l [spi0m0-rx l [spi0m0-cs1 l [spi0-1spi0m1-clk l[spi0m1-cs0 l[spi0m1-tx l[spi0m1-rx l[spi0m1-cs1 l[spi0-2spi0m2-clk l[,spi0m2-cs0 l[/spi0m2-tx l[-spi0m2-rx l[.i2s1i2s1-mclk lYi2s1-sclk lYi2s1-lrckrx lYi2s1-lrcktx lYi2s1-sdi lYi2s1-sdo lYi2s1-sdio1 lYi2s1-sdio2 lYi2s1-sdio3 lYi2s1-sleep lZZZZZZZZZi2s2-0i2s2m0-mclk lYi2s2m0-sclk lYi2s2m0-lrckrx lYi2s2m0-lrcktx lYi2s2m0-sdi lYi2s2m0-sdo lYi2s2m0-sleep` lZZZZZZi2s2-1i2s2m1-mclk lYi2s2m1-sclk lYi2sm1-lrckrx lYi2s2m1-lrcktx lYi2s2m1-sdi lYi2s2m1-sdo lYi2s2m1-sleepP lZZZZZspdif-0spdifm0-tx lYspdif-1spdifm1-tx lYspdif-2spdifm2-tx lYsdmmc0-0sdmmc0m0-pwren l\sdmmc0m0-pin l\sdmmc0-1sdmmc0m1-pwren l\sdmmc0m1-pin l\hsdmmc0sdmmc0-clk l]Fsdmmc0-cmd l^Gsdmmc0-dectn l\Hsdmmc0-wrprt l\sdmmc0-bus1 l^sdmmc0-bus4@ l^^^^Isdmmc0-pins l\\\\\\\\sdmmc0extsdmmc0ext-clk l_sdmmc0ext-cmd l\sdmmc0ext-wrprt l\sdmmc0ext-dectn l\sdmmc0ext-bus1 l\sdmmc0ext-bus4@ l\\\\sdmmc0ext-pins l\\\\\\\\sdmmc1sdmmc1-clk l ]sdmmc1-cmd l ^sdmmc1-pwren l^sdmmc1-wrprt l^sdmmc1-dectn l^sdmmc1-bus1 l^sdmmc1-bus4@ l^^^^sdmmc1-pins l \ \\\\\\\\emmcemmc-clk l`Kemmc-cmd laLemmc-pwren lYemmc-rstnout lYemmc-bus1 laemmc-bus4@ laaaaemmc-bus8 laaaaaaaaMpwm0pwm0-pin lY0pwm1pwm1-pin lY1pwm2pwm2-pin lY2pwmirpwmir-pin lY3gmac-1rgmiim1-pins` l ] __]___ _ _] ]__]]] ]_]]]]Prmiim1-pins lb`bbbb b b` ` Y YYYYYgmac2phyfephyled-speed10 lYfephyled-duplex lYfephyled-rxm1 lYUfephyled-txm1 lYfephyled-linkm1 lYVtsadc_pintsadc-int l Ytsadc-pin l Yhdmi_pinhdmi-cec lY?hdmi-hpd lcAcif-0dvp-d2d9-m0 lYYYYY Y Y YYYYYcif-1dvp-d2d9-m1 lYYYYYYYYYYYYephyeth-phy-int-pin lcQeth-phy-reset-pin lcRledsled-pin lYepmicpmic-int-l l[(usb3usb30-host-drv lYiwifiwifi-en lYjchosen zserial2:1500000n8adc-keys adc-keys d buttons button-recovery Recovery h 'external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Nleds gpio-ledsedefaultled-0  f heartbeatsdmmc-regulatorregulator-fixed gdefaulthvcc_sd= Jvcc-host-5v-regulatorregulator-fixed fdefaulti  vcc_host_5v)= )vcc-sysregulator-fixedvcc_sys)=OLK@gLK@)vcc-wifi-regulatorregulator-fixed gdefaultj vcc_wifi)=  compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1pmuio-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsvref-supplyinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-sd-highspeeddisable-wpvmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-handlephy-modephy-supplysnps,aalsnps,rxpbltx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosphy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltcolorlinux,default-triggergpiovin-supplyenable-active-high