Ð þí1‰8.((a-ð V2P-CA5s%# arm,vexpress,v2p-ca5sarm,vexpress+<Ksmb@8000000 simple-bus<K`W ^ o?´‚            !!""##$$%%&&''(())**motherboardV2M-P1rs1 arm,vexpress,v2m-p1simple-bus<K^Wflash@0 arm,vexpress-flashcfi-flash£§partitions arm,arm-firmware-suitepsram@100000000 arm,vexpress-psrammtd-ram £§ethernet@202000000 smsc,lan9118smsc,lan9115 £²½miiÆÓèû usb@203000000 nxp,usb-isp1761 £²iofpga@300000000 simple-bus<KW sysreg@10000 arm,vexpress-sysreg£<K W#gpio@8 arm,vexpress-sysreg,sys_led£+;#gpio@48 arm,vexpress-sysreg,sys_mci£H+;#gpio@4c arm,vexpress-sysreg,sys_flash£L+;sysctl@20000 arm,sp810arm,primecell£ GNrefclktimclkapb_pclkZ0gtimerclken0timerclken1timerclken2timerclken3 zŠ#i2c@30000 arm,versatile-i2c£<Kpcie-switch@60 idt,89hpes32h8£`aaci@40000 arm,pl041arm,primecell£² G Napb_pclkmmci@50000 arm,pl180arm,primecell£²  ¡ ª³·ÁGNmclkapb_pclkkmi@60000 arm,pl050arm,primecell£² GNKMIREFCLKapb_pclkkmi@70000 arm,pl050arm,primecell£² GNKMIREFCLKapb_pclkuart@90000 arm,pl011arm,primecell£ ²G Nuartclkapb_pclkuart@a0000 arm,pl011arm,primecell£ ²G Nuartclkapb_pclkuart@b0000 arm,pl011arm,primecell£ ²G Nuartclkapb_pclkuart@c0000 arm,pl011arm,primecell£ ²G Nuartclkapb_pclkwdt@f0000 arm,sp805arm,primecell£²GNwdogclkapb_pclktimer@110000 arm,sp804arm,primecell£²GNtimclken1timclken2apb_pclktimer@120000 arm,sp804arm,primecell£²GNtimclken1timclken2apb_pclki2c@160000 arm,versatile-i2c£<Kdvi-transmitter@39 sil,sii9022-tpisil,sii9022£9ports<Kport@0£endpointÍ # dvi-transmitter@60 sil,sii9022-cpisil,sii9022£`rtc@170000 arm,pl031arm,primecell£²G Napb_pclkcompact-flash@1a0000 arm,vexpress-cfata-generic£Ýclcd@1f0000 arm,pl111arm,primecell£ çcombined²G Nclcdclkapb_pclk÷7ù€ portendpointÍ  # fixed-regulator-0 regulator-fixed43V3C2Z [2Z s#clk24mhz fixed-clockZ‡n6 gv2m:clk24mhz#refclk1mhz fixed-clockZ‡B@gv2m:refclk1mhz#refclk32khz fixed-clockZ‡€gv2m:refclk32khz#leds gpio-ledsuser1—v2m:green:user1 ¤ heartbeatuser2—v2m:green:user2 ¤mmc0user3—v2m:green:user3 ¤cpu0user4—v2m:green:user4 ¤cpu1user5—v2m:green:user5 ¤cpu2user6—v2m:green:user6 ¤cpu3user7—v2m:green:user7 ¤cpu4user8—v2m:green:user8 ¤cpu5mcc arm,vexpress,config-bus³oscclk0 arm,vexpress-oscÎç}x@“‡Z gv2m:oscclk0oscclk1 arm,vexpress-oscÎçjepßÒ@Z gv2m:oscclk1# oscclk2 arm,vexpress-oscÎçn6n6Z gv2m:oscclk2# volt-vio arm,vexpress-voltÎ4VIOs—VIOtemp-mcc arm,vexpress-tempΗMCCreset arm,vexpress-resetÎmuxfpga arm,vexpress-muxfpgaÎshutdown arm,vexpress-shutdownÎreboot arm,vexpress-rebootÎ dvimode arm,vexpress-dvimodeÎ chosenaliases5ò/smb@8000000/motherboard/iofpga@300000000/uart@900005ú/smb@8000000/motherboard/iofpga@300000000/uart@a00005/smb@8000000/motherboard/iofpga@300000000/uart@b00005 /smb@8000000/motherboard/iofpga@300000000/uart@c00005/smb@8000000/motherboard/iofpga@300000000/i2c@1600004/smb@8000000/motherboard/iofpga@300000000/i2c@30000cpus<Kcpu@0cpu arm,cortex-a5£(cpu@1cpu arm,cortex-a5£(memory@80000000memory£€@reserved-memory<KWvram@18000000 shared-dma-pool£€9# hdlcd@2a110000 arm,hdlcd£* ²UGNpxlclkmemory-controller@2a150000 arm,pl341arm,primecell£*G Napb_pclkmemory-controller@2a190000 arm,pl354arm,primecell£*²VWG Napb_pclkscu@2c000000 arm,cortex-a5-scu£,Xtimer@2c000600 arm,cortex-a5-twd-timer£,  ² timer@2c0002006 arm,cortex-a5-global-timerarm,cortex-a9-global-timer£,  ² Gwatchdog@2c000620 arm,cortex-a5-twd-wdt£,  ²interrupt-controller@2c001000$ arm,cortex-a5-gicarm,cortex-a9-gic^<@£,,#cache-controller@2c0f0000 arm,pl310-cache£, ²TU#pmu arm,cortex-a5-pmu²DEdcc arm,vexpress,config-bus³oscclk0 arm,vexpress-oscÎçúð€õáZgoscclk0#oscclk1 arm,vexpress-oscÎçLK@úð€Zgoscclk1#oscclk2 arm,vexpress-oscÎçÄ´'Zgoscclk2oscclk3 arm,vexpress-oscÎçjep Õ³@Zgoscclk3#oscclk4 arm,vexpress-oscÎçÄ´Ä´Zgoscclk4oscclk5 arm,vexpress-oscÎç}x@“‡Zgoscclk5#temp-dcc arm,vexpress-tempΗDCChsb@40000000 simple-bus<K W@@^o`‚$%&' modelarm,hbiarm,vexpress,sitecompatibleinterrupt-parent#address-cells#size-cellsranges#interrupt-cellsinterrupt-map-maskinterrupt-maparm,v2m-memory-mapregbank-widthinterruptsphy-modereg-io-widthsmsc,irq-active-highsmsc,irq-push-pullvdd33a-supplyvddvario-supplyport1-otgphandlegpio-controller#gpio-cellsclocksclock-names#clock-cellsclock-output-namesassigned-clocksassigned-clock-parentscd-gpioswp-gpiosmax-frequencyvmmc-supplyremote-endpointreg-shiftinterrupt-namesmax-memory-bandwidthmemory-regionarm,pl11x,tft-r0g0b0-padsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onclock-frequencylabellinux,default-triggerarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangeserial0serial1serial2serial3i2c0i2c1device_typenext-level-cacheno-mapinterrupt-controllercache-level