[ppc64] Add VMX registers to sigcontext, from Steve Munroe
---
arch/ppc64/boot/ppc32-types.h | 4 ++++
include/asm-ppc64/elf.h | 19 ++++++++++++++++++-
include/asm-ppc64/ptrace.h | 25 +++++++++++++++++++++++++
include/asm-ppc64/sigcontext.h | 21 +++++++++++++++++++++
4 files changed, 68 insertions(+), 1 deletion(-)
diff -puN include/asm-ppc64/elf.h~ppc64-add_vmx include/asm-ppc64/elf.h
--- 25/include/asm-ppc64/elf.h~ppc64-add_vmx 2004-01-13 23:22:48.000000000 -0800
+++ 25-akpm/include/asm-ppc64/elf.h 2004-01-13 23:22:48.000000000 -0800
@@ -54,7 +54,7 @@
#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
#define ELF_NFPREG 33 /* includes fpscr */
-#define ELF_NVRREG 33 /* includes vscr */
+#define ELF_NVRREG 34 /* includes vscr */
typedef unsigned long elf_greg_t64;
typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
@@ -82,6 +82,23 @@ typedef elf_greg_t32 elf_gregset_t32[ELF
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
+/* Altivec registers */
+/*
+ * The entries with indexes 0-31 contain the corresponding vector registers.
+ * The entry with index 32 contains the vscr as the last word (offset 12)
+ * within the quadword. This allows the vscr to be stored as either a
+ * quadword (since it must be copied via a vector register to/from storage)
+ * or as a word. The entry with index 33 contains the vrsave as the first
+ * word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32
+ * ptrace interface. This allows signal handling and ptrace to use the same
+ * structures. This also simplifies the implementation of a bi-arch
+ * (combined (32- and 64-bit) gdb.
+ */
+typedef __vector128 elf_vrreg_t;
+typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
+
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
diff -puN include/asm-ppc64/ptrace.h~ppc64-add_vmx include/asm-ppc64/ptrace.h
--- 25/include/asm-ppc64/ptrace.h~ppc64-add_vmx 2004-01-13 23:22:48.000000000 -0800
+++ 25-akpm/include/asm-ppc64/ptrace.h 2004-01-13 23:22:48.000000000 -0800
@@ -130,6 +130,31 @@ struct pt_regs32 {
#define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
#endif
+#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
+#define PT_VSCR (PT_VR0 + 32*2 + 1)
+#define PT_VRSAVE (PT_VR0 + 33*2)
+
+#ifdef __KERNEL__
+#define PT_VR0_32 164 /* each Vector reg occupies 4 slots in 32-bit */
+#define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
+#define PT_VRSAVE_32 (PT_VR0 + 33*4)
+#endif
+
+/*
+ * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
+ * The transfer totals 34 quadword. Quadwords 0-31 contain the
+ * corresponding vector registers. Quadword 32 contains the vscr as the
+ * last word (offset 12) within that quadword. Quadword 33 contains the
+ * vrsave as the first word (offset 0) within the quadword.
+ *
+ * This definition of the VMX state is compatible with the current PPC32
+ * ptrace interface. This allows signal handling and ptrace to use the same
+ * structures. This also simplifies the implementation of a bi-arch
+ * (combined (32- and 64-bit) gdb.
+ */
+#define PTRACE_GETVRREGS 18
+#define PTRACE_SETVRREGS 19
+
/* Additional PTRACE requests implemented on PowerPC. */
#define PPC_PTRACE_GETREGS 0x99 /* Get GPRs 0 - 31 */
#define PPC_PTRACE_SETREGS 0x98 /* Set GPRs 0 - 31 */
diff -puN include/asm-ppc64/sigcontext.h~ppc64-add_vmx include/asm-ppc64/sigcontext.h
--- 25/include/asm-ppc64/sigcontext.h~ppc64-add_vmx 2004-01-13 23:22:48.000000000 -0800
+++ 25-akpm/include/asm-ppc64/sigcontext.h 2004-01-13 23:22:48.000000000 -0800
@@ -21,6 +21,27 @@ struct sigcontext {
struct pt_regs *regs;
elf_gregset_t gp_regs;
elf_fpregset_t fp_regs;
+/*
+ * To maintain compatibility with current implementations the sigcontext is
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords. This
+ * allows the array of vector registers to be quadword aligned independent of
+ * the alignment of the containing sigcontext or ucontext. It is the
+ * responsibility of the code setting the sigcontext to set this pointer to
+ * either NULL (if this processor does not support the VMX feature) or the
+ * address of the first quadword within the allocated (vmx_reserve) area.
+ *
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
+ * an array of 34 quadword entries (elf_vrregset_t). The entries with
+ * indexes 0-31 contain the corresponding vector registers. The entry with
+ * index 32 contains the vscr as the last word (offset 12) within the
+ * quadword. This allows the vscr to be stored as either a quadword (since
+ * it must be copied via a vector register to/from storage) or as a word.
+ * The entry with index 33 contains the vrsave as the first word (offset 0)
+ * within the quadword.
+ */
+ elf_vrreg_t *v_regs;
+ long vmx_reserve[ELF_NVRREG+ELF_NVRREG+1];
};
#endif /* _ASM_PPC64_SIGCONTEXT_H */
diff -puN arch/ppc64/boot/ppc32-types.h~ppc64-add_vmx arch/ppc64/boot/ppc32-types.h
--- 25/arch/ppc64/boot/ppc32-types.h~ppc64-add_vmx 2004-01-13 23:22:48.000000000 -0800
+++ 25-akpm/arch/ppc64/boot/ppc32-types.h 2004-01-13 23:22:48.000000000 -0800
@@ -25,6 +25,10 @@ typedef unsigned int u32;
typedef signed long long s64;
typedef unsigned long long u64;
+typedef struct {
+ __u32 u[4];
+} __attribute((aligned(16))) __vector128;
+
#define BITS_PER_LONG 32
#endif /* _PPC64_TYPES_H */
_