From: Pat Gefre <pfg@sgi.com>
Moved code out of pciio and into its own file - snia_if.c and renamed the
functions
pciio clean up
---
25-akpm/arch/ia64/sn/io/Makefile | 2
25-akpm/arch/ia64/sn/io/sn2/ml_iograph.c | 6
25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c | 4
25-akpm/arch/ia64/sn/io/sn2/pciio.c | 503 +++---------------------
25-akpm/arch/ia64/sn/io/snia_if.c | 108 +++++
25-akpm/arch/ia64/sn/kernel/setup.c | 6
25-akpm/include/asm-ia64/sn/pci/pciio.h | 38 +
25-akpm/include/asm-ia64/sn/pci/pciio_private.h | 18
25-akpm/include/asm-ia64/sn/sn2/sn_private.h | 1
9 files changed, 249 insertions(+), 437 deletions(-)
diff -puN arch/ia64/sn/io/Makefile~sn30 arch/ia64/sn/io/Makefile
--- 25/arch/ia64/sn/io/Makefile~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/arch/ia64/sn/io/Makefile Thu Jan 8 15:22:55 2004
@@ -9,5 +9,5 @@
# Makefile for the sn io routines.
#
-obj-y += xswitch.o sgi_io_sim.o cdl.o \
+obj-y += xswitch.o sgi_io_sim.o cdl.o snia_if.o \
io.o machvec/ drivers/ platform_init/ sn2/ hwgfs/
diff -puN arch/ia64/sn/io/sn2/ml_iograph.c~sn30 arch/ia64/sn/io/sn2/ml_iograph.c
--- 25/arch/ia64/sn/io/sn2/ml_iograph.c~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/ml_iograph.c Thu Jan 8 15:22:55 2004
@@ -182,16 +182,16 @@ assign_widgets_to_volunteers(vertex_hdl_
* hub that owned it in the prom.
*/
if (is_master_baseio_nasid_widget(nasid, widgetnum)) {
- extern nasid_t get_master_baseio_nasid(void);
+ extern nasid_t snia_get_master_baseio_nasid(void);
for (i=0; i<num_volunteer; i++) {
hubv = xvolinfo->xswitch_volunteer[i];
hubinfo_get(hubv, &hubinfo);
nasid = hubinfo->h_nasid;
- if (nasid == get_master_baseio_nasid())
+ if (nasid == snia_get_master_baseio_nasid())
goto do_assignment;
}
printk("Nasid == %d, console nasid == %d",
- nasid, get_master_baseio_nasid());
+ nasid, snia_get_master_baseio_nasid());
nasid = 0;
}
diff -puN arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c~sn30 arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
--- 25/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c Thu Jan 8 15:22:55 2004
@@ -1729,7 +1729,7 @@ pcibr_probe_slot_pic(bridge_t *bridge,
{
int rv;
picreg_t p_old_enable = (picreg_t)0, p_new_enable;
- extern int badaddr_val(volatile void *, int, volatile void *);
+ extern int snia_badaddr_val(volatile void *, int, volatile void *);
p_old_enable = bridge->p_int_enable_64;
p_new_enable = p_old_enable & ~(BRIDGE_IMR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT);
@@ -1742,7 +1742,7 @@ pcibr_probe_slot_pic(bridge_t *bridge,
bridge->p_int_rst_stat_64 = (BRIDGE_IRR_PCI_GRP_CLR | PIC_PCIX_GRP_CLR);
(void) bridge->b_wid_tflush; /* flushbus */
}
- rv = badaddr_val((void *) cfg, 4, valp);
+ rv = snia_badaddr_val((void *) cfg, 4, valp);
if (bridge->p_err_int_view_64 & (BRIDGE_ISR_PCI_MST_TIMEOUT | PIC_ISR_PCIX_MTOUT)) {
bridge->p_int_rst_stat_64 = BRIDGE_IRR_MULTI_CLR;
rv = 1; /* unoccupied slot */
diff -puN arch/ia64/sn/io/sn2/pciio.c~sn30 arch/ia64/sn/io/sn2/pciio.c
--- 25/arch/ia64/sn/io/sn2/pciio.c~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/arch/ia64/sn/io/sn2/pciio.c Thu Jan 8 15:22:55 2004
@@ -6,108 +6,11 @@
* Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
*/
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/xtalk/xbow.h> /* Must be before iograph.h to get MAX_PORT_NUM */
-#include <asm/sn/iograph.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/hcl_util.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pciio_private.h>
-#include <asm/sn/sn_sal.h>
-#include <asm/sn/io.h>
#include <asm/sn/pci/pci_bus_cvlink.h>
#include <asm/sn/simulator.h>
-#define DEBUG_PCIIO
-#undef DEBUG_PCIIO /* turn this on for yet more console output */
-
-
char pciio_info_fingerprint[] = "pciio_info";
-int
-badaddr_val(volatile void *addr, int len, volatile void *ptr)
-{
- int ret = 0;
- volatile void *new_addr;
-
- switch (len) {
- case 4:
- new_addr = (void *) addr;
- ret = ia64_sn_probe_io_slot((long)new_addr, len, (void *)ptr);
- break;
- default:
- printk(KERN_WARNING "badaddr_val given len %x but supports len of 4 only\n", len);
- }
-
- if (ret < 0)
- panic("badaddr_val: unexpected status (%d) in probing", ret);
- return(ret);
-
-}
-
-
-nasid_t
-get_console_nasid(void)
-{
- extern nasid_t console_nasid;
- extern nasid_t master_baseio_nasid;
-
- if (console_nasid < 0) {
- console_nasid = ia64_sn_get_console_nasid();
- if (console_nasid < 0) {
-// ZZZ What do we do if we don't get a console nasid on the hardware????
- if (IS_RUNNING_ON_SIMULATOR() )
- console_nasid = master_baseio_nasid;
- }
- }
- return console_nasid;
-}
-
-nasid_t
-get_master_baseio_nasid(void)
-{
- extern nasid_t master_baseio_nasid;
- extern char master_baseio_wid;
-
- if (master_baseio_nasid < 0) {
- master_baseio_nasid = ia64_sn_get_master_baseio_nasid();
-
- if ( master_baseio_nasid >= 0 ) {
- master_baseio_wid = WIDGETID_GET(KL_CONFIG_CH_CONS_INFO(master_baseio_nasid)->memory_base);
- }
- }
- return master_baseio_nasid;
-}
-
-int
-hub_error_devenable(vertex_hdl_t xconn_vhdl, int devnum, int error_code)
-{
- return(0);
-}
-
-void
-ioerror_dump(char *name, int error_code, int error_mode, ioerror_t *ioerror)
-{
-}
-
-/******
- ****** end hack defines ......
- ******/
-
-
-
-
/* =====================================================================
* PCI Generic Bus Provider
* Implement PCI provider operations. The pciio* layer provides a
@@ -116,111 +19,6 @@ ioerror_dump(char *name, int error_code,
*/
/* =====================================================================
- * Provider Function Location SHORTCUT
- *
- * On platforms with only one possible PCI provider, macros can be
- * set up at the top that cause the table lookups and indirections to
- * completely disappear.
- */
-
-
-/* =====================================================================
- * Function Table of Contents
- */
-
-#if !defined(DEV_FUNC)
-static pciio_provider_t *pciio_to_provider_fns(vertex_hdl_t dev);
-#endif
-
-pciio_piomap_t pciio_piomap_alloc(vertex_hdl_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
-void pciio_piomap_free(pciio_piomap_t);
-caddr_t pciio_piomap_addr(pciio_piomap_t, iopaddr_t, size_t);
-
-void pciio_piomap_done(pciio_piomap_t);
-caddr_t pciio_piotrans_addr(vertex_hdl_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-caddr_t pciio_pio_addr(vertex_hdl_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, pciio_piomap_t *, unsigned);
-
-iopaddr_t pciio_piospace_alloc(vertex_hdl_t, device_desc_t, pciio_space_t, size_t, size_t);
-void pciio_piospace_free(vertex_hdl_t, pciio_space_t, iopaddr_t, size_t);
-
-pciio_dmamap_t pciio_dmamap_alloc(vertex_hdl_t, device_desc_t, size_t, unsigned);
-void pciio_dmamap_free(pciio_dmamap_t);
-iopaddr_t pciio_dmamap_addr(pciio_dmamap_t, paddr_t, size_t);
-void pciio_dmamap_done(pciio_dmamap_t);
-iopaddr_t pciio_dmatrans_addr(vertex_hdl_t, device_desc_t, paddr_t, size_t, unsigned);
-void pciio_dmamap_drain(pciio_dmamap_t);
-void pciio_dmaaddr_drain(vertex_hdl_t, paddr_t, size_t);
-void pciio_dmalist_drain(vertex_hdl_t, alenlist_t);
-iopaddr_t pciio_dma_addr(vertex_hdl_t, device_desc_t, paddr_t, size_t, pciio_dmamap_t *, unsigned);
-
-pciio_intr_t pciio_intr_alloc(vertex_hdl_t, device_desc_t, pciio_intr_line_t, vertex_hdl_t);
-void pciio_intr_free(pciio_intr_t);
-int pciio_intr_connect(pciio_intr_t, intr_func_t, intr_arg_t);
-void pciio_intr_disconnect(pciio_intr_t);
-vertex_hdl_t pciio_intr_cpu_get(pciio_intr_t);
-
-void pciio_slot_func_to_name(char *, pciio_slot_t, pciio_function_t);
-
-void pciio_provider_startup(vertex_hdl_t);
-void pciio_provider_shutdown(vertex_hdl_t);
-
-pciio_endian_t pciio_endian_set(vertex_hdl_t, pciio_endian_t, pciio_endian_t);
-pciio_priority_t pciio_priority_set(vertex_hdl_t, pciio_priority_t);
-vertex_hdl_t pciio_intr_dev_get(pciio_intr_t);
-
-vertex_hdl_t pciio_pio_dev_get(pciio_piomap_t);
-pciio_slot_t pciio_pio_slot_get(pciio_piomap_t);
-pciio_space_t pciio_pio_space_get(pciio_piomap_t);
-iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t);
-ulong pciio_pio_mapsz_get(pciio_piomap_t);
-caddr_t pciio_pio_kvaddr_get(pciio_piomap_t);
-
-vertex_hdl_t pciio_dma_dev_get(pciio_dmamap_t);
-pciio_slot_t pciio_dma_slot_get(pciio_dmamap_t);
-
-pciio_info_t pciio_info_chk(vertex_hdl_t);
-pciio_info_t pciio_info_get(vertex_hdl_t);
-void pciio_info_set(vertex_hdl_t, pciio_info_t);
-vertex_hdl_t pciio_info_dev_get(pciio_info_t);
-pciio_slot_t pciio_info_slot_get(pciio_info_t);
-pciio_function_t pciio_info_function_get(pciio_info_t);
-pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t);
-pciio_device_id_t pciio_info_device_id_get(pciio_info_t);
-vertex_hdl_t pciio_info_master_get(pciio_info_t);
-arbitrary_info_t pciio_info_mfast_get(pciio_info_t);
-pciio_provider_t *pciio_info_pops_get(pciio_info_t);
-error_handler_f *pciio_info_efunc_get(pciio_info_t);
-error_handler_arg_t *pciio_info_einfo_get(pciio_info_t);
-pciio_space_t pciio_info_bar_space_get(pciio_info_t, int);
-iopaddr_t pciio_info_bar_base_get(pciio_info_t, int);
-size_t pciio_info_bar_size_get(pciio_info_t, int);
-iopaddr_t pciio_info_rom_base_get(pciio_info_t);
-size_t pciio_info_rom_size_get(pciio_info_t);
-
-int pciio_attach(vertex_hdl_t);
-
-void pciio_provider_register(vertex_hdl_t, pciio_provider_t *pciio_fns);
-void pciio_provider_unregister(vertex_hdl_t);
-pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t);
-
-int pciio_driver_register(pciio_vendor_id_t, pciio_device_id_t, char *driver_prefix, unsigned);
-
-vertex_hdl_t pciio_device_register(vertex_hdl_t, vertex_hdl_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
-
-void pciio_device_unregister(vertex_hdl_t);
-pciio_info_t pciio_device_info_new(pciio_info_t, vertex_hdl_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
-void pciio_device_info_free(pciio_info_t);
-vertex_hdl_t pciio_device_info_register(vertex_hdl_t, pciio_info_t);
-void pciio_device_info_unregister(vertex_hdl_t, pciio_info_t);
-int pciio_device_attach(vertex_hdl_t, int);
-int pciio_device_detach(vertex_hdl_t, int);
-void pciio_error_register(vertex_hdl_t, error_handler_f *, error_handler_arg_t);
-
-int pciio_reset(vertex_hdl_t);
-int pciio_write_gather_flush(vertex_hdl_t);
-int pciio_slot_inuse(vertex_hdl_t);
-
-/* =====================================================================
* Provider Function Location
*
* If there is more than one possible provider for
@@ -230,8 +28,6 @@ int pciio_slot_inuse
* appropriately named member.
*/
-#if !defined(DEV_FUNC)
-
pciio_provider_t *
pciio_to_provider_fns(vertex_hdl_t dev)
{
@@ -253,13 +49,10 @@ pciio_to_provider_fns(vertex_hdl_t dev)
}
}
- if (provider_fns == NULL)
-#if defined(SUPPORT_PRINTING_V_FORMAT)
- panic("%v: provider_fns == NULL", dev);
-#else
- panic("0x%p: provider_fns == NULL", (void *)dev);
-#endif
-
+ if (provider_fns == NULL) {
+ char devname[MAXDEVNAME];
+ panic("%s: provider_fns == NULL", vertex_to_name(dev, devname, MAXDEVNAME));
+ }
return provider_fns;
}
@@ -268,7 +61,6 @@ pciio_to_provider_fns(vertex_hdl_t dev)
#define CAST_PIOMAP(x) ((pciio_piomap_t)(x))
#define CAST_DMAMAP(x) ((pciio_dmamap_t)(x))
#define CAST_INTR(x) ((pciio_intr_t)(x))
-#endif
/*
* Many functions are not passed their vertex
@@ -745,50 +537,6 @@ pciio_provider_shutdown(vertex_hdl_t pci
}
/*
- * Specify endianness constraints. The driver tells us what the device
- * does and how it would like to see things in memory. We reply with
- * how things will actually appear in memory.
- */
-pciio_endian_t
-pciio_endian_set(vertex_hdl_t dev,
- pciio_endian_t device_end,
- pciio_endian_t desired_end)
-{
- ASSERT((device_end == PCIDMA_ENDIAN_BIG) || (device_end == PCIDMA_ENDIAN_LITTLE));
- ASSERT((desired_end == PCIDMA_ENDIAN_BIG) || (desired_end == PCIDMA_ENDIAN_LITTLE));
-
-#if DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
- printk(KERN_ALERT "%v: pciio_endian_set is going away.\n"
- "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
- "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
- dev);
-#else
- printk(KERN_ALERT "0x%x: pciio_endian_set is going away.\n"
- "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
- "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
- dev);
-#endif
-#endif
-
- return DEV_FUNC(dev, endian_set)
- (dev, device_end, desired_end);
-}
-
-/*
- * Specify PCI arbitration priority.
- */
-pciio_priority_t
-pciio_priority_set(vertex_hdl_t dev,
- pciio_priority_t device_prio)
-{
- ASSERT((device_prio == PCI_PRIO_HIGH) || (device_prio == PCI_PRIO_LOW));
-
- return DEV_FUNC(dev, priority_set)
- (dev, device_prio);
-}
-
-/*
* Read value of configuration register
*/
uint64_t
@@ -857,71 +605,6 @@ pciio_reset(vertex_hdl_t dev)
return DEV_FUNC(dev, reset) (dev);
}
-/*
- * flush write gather buffers
- */
-int
-pciio_write_gather_flush(vertex_hdl_t dev)
-{
- return DEV_FUNC(dev, write_gather_flush) (dev);
-}
-
-vertex_hdl_t
-pciio_intr_dev_get(pciio_intr_t pciio_intr)
-{
- return (pciio_intr->pi_dev);
-}
-
-/****** Generic crosstalk pio interfaces ******/
-vertex_hdl_t
-pciio_pio_dev_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_dev);
-}
-
-pciio_slot_t
-pciio_pio_slot_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_slot);
-}
-
-pciio_space_t
-pciio_pio_space_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_space);
-}
-
-iopaddr_t
-pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_pciaddr);
-}
-
-ulong
-pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_mapsz);
-}
-
-caddr_t
-pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap)
-{
- return (pciio_piomap->pp_kvaddr);
-}
-
-/****** Generic crosstalk dma interfaces ******/
-vertex_hdl_t
-pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap)
-{
- return (pciio_dmamap->pd_dev);
-}
-
-pciio_slot_t
-pciio_dma_slot_get(pciio_dmamap_t pciio_dmamap)
-{
- return (pciio_dmamap->pd_slot);
-}
-
/****** Generic pci slot information interfaces ******/
pciio_info_t
@@ -950,6 +633,25 @@ pciio_info_get(vertex_hdl_t pciio)
return pciio_info;
}
+/*
+ * Given a vertex_hdl_t, return the pciio_info_t from the host device - that
+ * is, the device plugged into the slot on the host bus.
+ */
+
+pciio_info_t
+pciio_hostinfo_get(vertex_hdl_t pciio)
+{
+ pciio_info_t pciio_info;
+
+ pciio_info = pciio_info_get(pciio);
+ if (pciio_info && (pciio_info->c_vertex != pciio_info->c_hostvertex)) {
+ pciio_info = pciio_info_get(pciio_info->c_hostvertex);
+ }
+
+ return pciio_info;
+}
+
+
void
pciio_info_set(vertex_hdl_t pciio, pciio_info_t pciio_info)
{
@@ -971,12 +673,34 @@ pciio_info_dev_get(pciio_info_t pciio_in
return (pciio_info->c_vertex);
}
+vertex_hdl_t
+pciio_info_hostdev_get(pciio_info_t pciio_info)
+{
+ return (pciio_info->c_hostvertex);
+}
+
+/*ARGSUSED*/
+pciio_bus_t
+pciio_info_bus_get(pciio_info_t pciio_info)
+{
+ return (pciio_info->c_bus);
+}
+
pciio_slot_t
pciio_info_slot_get(pciio_info_t pciio_info)
{
return (pciio_info->c_slot);
}
+pciio_slot_t
+pciio_info_hostslot_get(pciio_info_t pciio_info)
+{
+ vertex_hdl_t host_vhdl = pciio_info_hostdev_get(pciio_info);
+ pciio_info_t host_info = pciio_info_get(host_vhdl);
+
+ return (pciio_info_slot_get(host_info));
+}
+
pciio_function_t
pciio_info_function_get(pciio_info_t pciio_info)
{
@@ -1013,49 +737,30 @@ pciio_info_pops_get(pciio_info_t pciio_i
return (pciio_info->c_pops);
}
-error_handler_f *
-pciio_info_efunc_get(pciio_info_t pciio_info)
-{
- return (pciio_info->c_efunc);
-}
-
-error_handler_arg_t *
-pciio_info_einfo_get(pciio_info_t pciio_info)
-{
- return (pciio_info->c_einfo);
-}
-
-pciio_space_t
-pciio_info_bar_space_get(pciio_info_t info, int win)
-{
- return info->c_window[win].w_space;
-}
-
-iopaddr_t
-pciio_info_bar_base_get(pciio_info_t info, int win)
+int
+pciio_businfo_multi_master_get(pciio_businfo_t businfo)
{
- return info->c_window[win].w_base;
+ return businfo->bi_multi_master;
}
-size_t
-pciio_info_bar_size_get(pciio_info_t info, int win)
+pciio_asic_type_t
+pciio_businfo_asic_type_get(pciio_businfo_t businfo)
{
- return info->c_window[win].w_size;
+ return businfo->bi_asic_type;
}
-iopaddr_t
-pciio_info_rom_base_get(pciio_info_t info)
+pciio_bus_type_t
+pciio_businfo_bus_type_get(pciio_businfo_t businfo)
{
- return info->c_rbase;
+ return businfo->bi_bus_type;
}
-size_t
-pciio_info_rom_size_get(pciio_info_t info)
+pciio_bus_speed_t
+pciio_businfo_bus_speed_get(pciio_businfo_t businfo)
{
- return info->c_rsize;
+ return businfo->bi_bus_speed;
}
-
/* =====================================================================
* GENERIC PCI INITIALIZATION FUNCTIONS
*/
@@ -1069,11 +774,8 @@ int
pciio_attach(vertex_hdl_t pciio)
{
#if DEBUG && ATTACH_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
- printk("%v: pciio_attach\n", pciio);
-#else
- printk("0x%x: pciio_attach\n", pciio);
-#endif
+ char devname[MAXDEVNAME];
+ printk("%s: pciio_attach\n", vertex_to_name(pciio, devname, MAXDEVNAME));
#endif
return 0;
}
@@ -1111,37 +813,6 @@ pciio_provider_fns_get(vertex_hdl_t prov
return (pciio_provider_t *) ainfo;
}
-/*ARGSUSED4 */
-int
-pciio_driver_register(
- pciio_vendor_id_t vendor_id,
- pciio_device_id_t device_id,
- char *driver_prefix,
- unsigned flags)
-{
- return(0);
-}
-
-vertex_hdl_t
-pciio_device_register(
- vertex_hdl_t connectpt, /* vertex for /hw/.../pciio/%d */
- vertex_hdl_t master, /* card's master ASIC (PCI provider) */
- pciio_slot_t slot, /* card's slot */
- pciio_function_t func, /* card's func */
- pciio_vendor_id_t vendor_id,
- pciio_device_id_t device_id)
-{
- return pciio_device_info_register
- (connectpt, pciio_device_info_new (NULL, master, slot, func,
- vendor_id, device_id));
-}
-
-void
-pciio_device_unregister(vertex_hdl_t pconn)
-{
- DEV_FUNC(pconn,device_unregister)(pconn);
-}
-
pciio_info_t
pciio_device_info_new(
pciio_info_t pciio_info,
@@ -1288,14 +959,26 @@ pciio_device_win_alloc(struct resource *
{
struct resource *new_res;
- int status = 0;
+ int status;
new_res = (struct resource *) kmalloc( sizeof(struct resource), GFP_KERNEL);
+ if (!new_res)
+ return 0;
- status = allocate_resource( root_resource, new_res,
+ if (start > 0) {
+ status = allocate_resource( root_resource, new_res,
+ size, start /* Min start addr. */,
+ (start + size) - 1, 1,
+ NULL, NULL);
+ } else {
+ if (size > align)
+ align = size;
+ status = allocate_resource( root_resource, new_res,
size, align /* Min start addr. */,
root_resource->end, align,
NULL, NULL);
+ }
+
if (status) {
kfree(new_res);
return((iopaddr_t) NULL);
@@ -1321,8 +1004,7 @@ pciio_device_win_alloc(struct resource *
void
pciio_device_win_free(pciio_win_alloc_t win_alloc)
{
-
- int status = 0;
+ int status;
if (win_alloc->wa_resource) {
status = release_resource(win_alloc->wa_resource);
@@ -1386,39 +1068,14 @@ pciio_slot_inuse(vertex_hdl_t pconn_vhdl
int
pciio_info_type1_get(pciio_info_t pci_info)
{
- return(0);
+ return (pci_info->c_type1);
}
-/*
- * XXX: should probably be called __sn2_pci_rrb_alloc
- */
-/* used by qla1280 */
-int
-snia_pcibr_rrb_alloc(struct pci_dev *pci_dev,
- int *count_vchan0,
- int *count_vchan1)
+pciio_businfo_t
+pciio_businfo_get(vertex_hdl_t conn)
{
- vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
-
- return pcibr_rrb_alloc(dev, count_vchan0, count_vchan1);
-}
-EXPORT_SYMBOL(snia_pcibr_rrb_alloc);
+ pciio_info_t info;
-/*
- * XXX: interface should be more like
- *
- * int __sn2_pci_enable_bwswap(struct pci_dev *dev);
- * void __sn2_pci_disable_bswap(struct pci_dev *dev);
- */
-/* used by ioc4 ide */
-pciio_endian_t
-snia_pciio_endian_set(struct pci_dev *pci_dev,
- pciio_endian_t device_end,
- pciio_endian_t desired_end)
-{
- vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
-
- return DEV_FUNC(dev, endian_set)
- (dev, device_end, desired_end);
+ info = pciio_info_get(conn);
+ return DEV_FUNC(conn, businfo_get)(conn);
}
-EXPORT_SYMBOL(snia_pciio_endian_set);
diff -puN /dev/null arch/ia64/sn/io/snia_if.c
--- /dev/null Thu Apr 11 07:25:15 2002
+++ 25-akpm/arch/ia64/sn/io/snia_if.c Thu Jan 8 15:22:55 2004
@@ -0,0 +1,108 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
+
+extern pciio_provider_t *pciio_to_provider_fns(vertex_hdl_t dev);
+
+int
+snia_badaddr_val(volatile void *addr, int len, volatile void *ptr)
+{
+ int ret = 0;
+ volatile void *new_addr;
+
+ switch (len) {
+ case 4:
+ new_addr = (void *) addr;
+ ret = ia64_sn_probe_io_slot((long) new_addr, len, (void *) ptr);
+ break;
+ default:
+ printk(KERN_WARNING
+ "snia_badaddr_val given len %x but supports len of 4 only\n",
+ len);
+ }
+
+ if (ret < 0)
+ panic("snia_badaddr_val: unexpected status (%d) in probing",
+ ret);
+ return (ret);
+
+}
+
+nasid_t
+snia_get_console_nasid(void)
+{
+ extern nasid_t console_nasid;
+ extern nasid_t master_baseio_nasid;
+
+ if (console_nasid < 0) {
+ console_nasid = ia64_sn_get_console_nasid();
+ if (console_nasid < 0) {
+// ZZZ What do we do if we don't get a console nasid on the hardware????
+ if (IS_RUNNING_ON_SIMULATOR())
+ console_nasid = master_baseio_nasid;
+ }
+ }
+ return console_nasid;
+}
+
+nasid_t
+snia_get_master_baseio_nasid(void)
+{
+ extern nasid_t master_baseio_nasid;
+ extern char master_baseio_wid;
+
+ if (master_baseio_nasid < 0) {
+ master_baseio_nasid = ia64_sn_get_master_baseio_nasid();
+
+ if (master_baseio_nasid >= 0) {
+ master_baseio_wid =
+ WIDGETID_GET(KL_CONFIG_CH_CONS_INFO
+ (master_baseio_nasid)->memory_base);
+ }
+ }
+ return master_baseio_nasid;
+}
+
+/*
+ * XXX: should probably be called __sn2_pci_rrb_alloc
+ * used by qla1280
+ */
+
+int
+snia_pcibr_rrb_alloc(struct pci_dev *pci_dev,
+ int *count_vchan0, int *count_vchan1)
+{
+ vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
+
+ return pcibr_rrb_alloc(dev, count_vchan0, count_vchan1);
+}
+
+/*
+ * XXX: interface should be more like
+ *
+ * int __sn2_pci_enable_bwswap(struct pci_dev *dev);
+ * void __sn2_pci_disable_bswap(struct pci_dev *dev);
+ */
+/* used by ioc4 ide */
+
+pciio_endian_t
+snia_pciio_endian_set(struct pci_dev * pci_dev,
+ pciio_endian_t device_end, pciio_endian_t desired_end)
+{
+ vertex_hdl_t dev = PCIDEV_VERTEX(pci_dev);
+
+ return ((pciio_to_provider_fns(dev))->endian_set)
+ (dev, device_end, desired_end);
+}
+
+EXPORT_SYMBOL(snia_pciio_endian_set);
+EXPORT_SYMBOL(snia_pcibr_rrb_alloc);
diff -puN arch/ia64/sn/kernel/setup.c~sn30 arch/ia64/sn/kernel/setup.c
--- 25/arch/ia64/sn/kernel/setup.c~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/arch/ia64/sn/kernel/setup.c Thu Jan 8 15:22:55 2004
@@ -218,7 +218,7 @@ sn_setup(char **cmdline_p)
long status, ticks_per_sec, drift;
int pxm;
int major = sn_sal_rev_major(), minor = sn_sal_rev_minor();
- extern nasid_t get_master_baseio_nasid(void);
+ extern nasid_t snia_get_master_baseio_nasid(void);
extern void sn_cpu_init(void);
MAX_DMA_ADDRESS = PAGE_OFFSET + MAX_PHYS_MEMORY;
@@ -241,8 +241,8 @@ sn_setup(char **cmdline_p)
}
master_nasid = get_nasid();
- (void)get_console_nasid();
- (void)get_master_baseio_nasid();
+ (void)snia_get_console_nasid();
+ (void)snia_get_master_baseio_nasid();
status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift);
if (status != 0 || ticks_per_sec < 100000) {
diff -puN include/asm-ia64/sn/pci/pciio.h~sn30 include/asm-ia64/sn/pci/pciio.h
--- 25/include/asm-ia64/sn/pci/pciio.h~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/include/asm-ia64/sn/pci/pciio.h Thu Jan 8 15:22:55 2004
@@ -197,6 +197,31 @@ typedef enum pciio_endian_e {
} pciio_endian_t;
/*
+ * Generic PCI bus information
+ */
+typedef enum pciio_asic_type_e {
+ PCIIO_ASIC_TYPE_UNKNOWN,
+ PCIIO_ASIC_TYPE_MACE,
+ PCIIO_ASIC_TYPE_BRIDGE,
+ PCIIO_ASIC_TYPE_XBRIDGE,
+ PCIIO_ASIC_TYPE_PIC,
+} pciio_asic_type_t;
+
+typedef enum pciio_bus_type_e {
+ PCIIO_BUS_TYPE_UNKNOWN,
+ PCIIO_BUS_TYPE_PCI,
+ PCIIO_BUS_TYPE_PCIX
+} pciio_bus_type_t;
+
+typedef enum pciio_bus_speed_e {
+ PCIIO_BUS_SPEED_UNKNOWN,
+ PCIIO_BUS_SPEED_33,
+ PCIIO_BUS_SPEED_66,
+ PCIIO_BUS_SPEED_100,
+ PCIIO_BUS_SPEED_133
+} pciio_bus_speed_t;
+
+/*
* Interface to set PCI arbitration priority for devices that require
* realtime characteristics. pciio_priority_set is used to switch a
* device between the PCI high-priority arbitration ring and the low
@@ -221,6 +246,9 @@ typedef struct pciio_piospace_s *pciio_p
typedef struct pciio_win_info_s *pciio_win_info_t;
typedef struct pciio_win_map_s *pciio_win_map_t;
typedef struct pciio_win_alloc_s *pciio_win_alloc_t;
+typedef struct pciio_bus_map_s *pciio_bus_map_t;
+typedef struct pciio_businfo_s *pciio_businfo_t;
+
/* PIO MANAGEMENT */
@@ -451,6 +479,9 @@ pciio_driver_unreg_callback_f (vertex_hd
typedef int
pciio_device_unregister_f (vertex_hdl_t conn);
+typedef pciio_businfo_t
+pciio_businfo_get_f (vertex_hdl_t conn);
+
/*
* Adapters that provide a PCI interface adhere to this software interface.
*/
@@ -499,6 +530,9 @@ typedef struct pciio_provider_s {
pciio_driver_reg_callback_f *driver_reg_callback;
pciio_driver_unreg_callback_f *driver_unreg_callback;
pciio_device_unregister_f *device_unregister;
+
+ /* GENERIC BUS INFO */
+ pciio_businfo_get_f *businfo_get;
} pciio_provider_t;
/* PCI devices use these standard PCI provider interfaces */
@@ -743,8 +777,4 @@ sn_pci_set_vchan(struct pci_dev *pci_dev
int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr);
nasid_t snia_get_console_nasid(void);
nasid_t snia_get_master_baseio_nasid(void);
-/* XXX: should probably be called __sn2_pci_rrb_alloc */
-int snia_pcibr_rrb_alloc(struct pci_dev *pci_dev, int *count_vchan0, int *count_vchan1);
-pciio_endian_t snia_pciio_endian_set(struct pci_dev *pci_dev,
- pciio_endian_t device_end, pciio_endian_t desired_end);
#endif /* _ASM_IA64_SN_PCI_PCIIO_H */
diff -puN include/asm-ia64/sn/pci/pciio_private.h~sn30 include/asm-ia64/sn/pci/pciio_private.h
--- 25/include/asm-ia64/sn/pci/pciio_private.h~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/include/asm-ia64/sn/pci/pciio_private.h Thu Jan 8 15:22:55 2004
@@ -59,6 +59,20 @@ struct pciio_intr_s {
#define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */
/*
+ * Generic PCI bus information
+ */
+struct pciio_businfo_s {
+ int bi_multi_master;/* Bus provider supports multiple */
+ /* dma masters behind a single slot. */
+ /* Needed to work around a thrashing */
+ /* issue in SGI Bridge ASIC and */
+ /* its derivatives. */
+ pciio_asic_type_t bi_asic_type; /* PCI ASIC type */
+ pciio_bus_type_t bi_bus_type; /* PCI bus type */
+ pciio_bus_speed_t bi_bus_speed; /* PCI bus speed */
+};
+
+/*
* Some PCI provider implementations keep track of PCI window Base Address
* Register (BAR) address range assignment via the rmalloc()/rmfree() arena
* management routines. These implementations use the following data
@@ -98,6 +112,7 @@ struct pciio_win_alloc_s {
struct pciio_info_s {
char *c_fingerprint;
vertex_hdl_t c_vertex; /* back pointer to vertex */
+ vertex_hdl_t c_hostvertex;/* top most device in tree */
pciio_bus_t c_bus; /* which bus the card is in */
pciio_slot_t c_slot; /* which slot the card is in */
pciio_function_t c_func; /* which func (on multi-func cards) */
@@ -111,6 +126,8 @@ struct pciio_info_s {
struct pciio_win_info_s { /* state of BASE regs */
pciio_space_t w_space;
+ char w_code; /* low 4 bits of MEM BAR */
+ /* low 2 bits of IO BAR */
iopaddr_t w_base;
size_t w_size;
int w_devio_index; /* DevIO[] register used to
@@ -121,6 +138,7 @@ struct pciio_info_s {
#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */
#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */
pciio_piospace_t c_piospace; /* additional I/O spaces allocated */
+ int c_type1; /* use type1 addressing */
};
extern char pciio_info_fingerprint[];
diff -puN include/asm-ia64/sn/sn2/sn_private.h~sn30 include/asm-ia64/sn/sn2/sn_private.h
--- 25/include/asm-ia64/sn/sn2/sn_private.h~sn30 Thu Jan 8 15:22:55 2004
+++ 25-akpm/include/asm-ia64/sn/sn2/sn_private.h Thu Jan 8 15:22:55 2004
@@ -22,7 +22,6 @@ extern void cpu_unenable(cpuid_t);
extern nasid_t get_lowest_nasid(void);
extern __psunsigned_t get_master_bridge_base(void);
extern int check_nasid_equiv(nasid_t, nasid_t);
-extern nasid_t get_console_nasid(void);
extern char get_console_pcislot(void);
extern int is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
_